k4b2g0446e Samsung Semiconductor, Inc., k4b2g0446e Datasheet - Page 39

• Manufacturer Part Number: k4b2g0446e
• Description: Ddp 2gb E-die Ddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4B2G0446E
K4B2G0846E
13.0 Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600
13.1 Clock specification
The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in malfunction of the DDR3
SDRAM device.
13.1.1 Definition for tCK (avg)
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to
rising edge.
13.1.2 Definition for tCK (abs)
tCK(abs) is the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tCK(abs) is not subject to production test.
13.1.3 Definition for tCH(avg) and tCL(avg)
tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses:
tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses:
13.1.4 Definition for note for tJIT(per), tJIT(per,Ick)
tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = min/max of {tCKi-tCK(avg) where i=1 to 200}
tJIT(per) defines the single period jitter when the DLL is already locked.
tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.
tJIT(per) and tJIT(per,lck) are not subject to production test.
13.1.5 Definition for note for tJIT(cc), tJIT(cc,Ick)
tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles: tJIT(cc) = Max of {tCKi+1-tCKi}
tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.
tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.
tJIT(cc) and tJIT(cc,lck) are not subject to production test.
13.1.6 Definition for tERR(nper)
tERR is defined as the cumulative error across n multiple consecutive cycles from tCK(avg). tERR is not subject to production test.
∑
∑
j=1
j=1
N
N
tCHj
tCKj
N x tCK(avg)
N
N=200
N=200
Page 39 of 59
∑
j=1
N
tCLj
N x tCK(avg)
DDP 2Gb DDR3 SDRAM
Rev. 1.0 March 2009
N=200