k4b2g0446e Samsung Semiconductor, Inc., k4b2g0446e Datasheet - Page 24
![no-image](/images/no-image-200.jpg)
k4b2g0446e
Manufacturer Part Number
k4b2g0446e
Description
Ddp 2gb E-die Ddr3 Sdram
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.K4B2G0446E.pdf
(59 pages)
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K4B2G0446E
K4B2G0846E
Note :
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage
2. The tolerance limits are specified under the condition that V
3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5XV
4. Not a specification requirement, but a design guide line
5. Measurement definition for RTT:
6. Measurement definition for V
9.8.2 ODT Temperature and Voltage sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to table below
∆T = T - T(@calibration); ∆V = V
[ Table 26 ] ODT Sensitivity Definition
[ Table 27 ] ODT Voltage and Temperature Sensitivity
These parameters may not be subject to production test. They are verified by design and characterization.
Apply V
changes after calibration, see following section on voltage and temperature sensitivity
spec shown above, e.g. calibration at 0.2XV
IH
(AC) to pin under test and measure current I(V
dR
dR
RTT
TT
TT
dV
dT
M
and
DDQ
∆
- V
V
M
DDQ
0.9 - dR
: Measure voltage (V
(@calibration); V
DDQ
TT
and 0.8XV
dT * |
RTT
∆ V
Min
Min
∆T| - dR
0
0
IH
M
(AC)), then apply V
=
=
DDQ
DDQ
DD
M
TT
) at test pin (midpoint) with no load
.
dV * |∆V|
Page 24 of 59
= V
= V
DD
DDQ
V
2 x
I(V
V
IH
DDQ
and that V
IH
(AC) - V
V
(AC)) - I(V
M
IL
(AC) to pin under test and measure current I(V
- 1
IL
SSQ
DDQ
(AC)
IL
1.6 + dR
. Other calibration schemes may be used to achieve the linearity
= V
(AC))
x 100
SS
TT
dT * |
DDP 2Gb DDR3 SDRAM
Max
Max
0.15
1.5
∆T| + dR
TT
dV * |∆V|
Rev. 1.0 March 2009
IL
(AC)) perspectively
RZQ/2,4,6,8,12
%/mV
Units
Units
%/°C
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