k4b2g0446e Samsung Semiconductor, Inc., k4b2g0446e Datasheet - Page 32
![no-image](/images/no-image-200.jpg)
k4b2g0446e
Manufacturer Part Number
k4b2g0446e
Description
Ddp 2gb E-die Ddr3 Sdram
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.K4B2G0446E.pdf
(59 pages)
- Current page: 32 of 59
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K4B2G0446E
K4B2G0846E
[ Table 32 ] IDD0 Measurement - Loop Pattern
Note :
1. DM must be driben LOW all the time. DQS, DQS are MID-LEVEL.
2. DQ signals are MID-LEVEL.
0
1
2
3
4
5
6
7
1*nRC + nRAS
1*nRC + 1, 2
1*nRC + 3, 4
1*nRC + 0
10*nRC
12*nRC
14*nRC
2*nRC
4*nRC
6*nRC
8*nRC
nRAS
1,2
3,4
...
...
...
...
0
repeat pattern 1...4 until nRAS - 1, truncate if necessary
repeat pattern 1...4 until nRC - 1, truncate if necessary
repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary
repeat 1...4 until 2*nRC - 1, truncate if necessary
repeat Sub-Loop 0, use BA[2:0] = 1 instead
repeat Sub-Loop 0, use BA[2:0] = 2 instead
repeat Sub-Loop 0, use BA[2:0] = 3 instead
repeat Sub-Loop 0, use BA[2:0] = 4 instead
repeat Sub-Loop 0, use BA[2:0] = 5 instead
repeat Sub-Loop 0, use BA[2:0] = 6 instead
repeat Sub-Loop 0, use BA[2:0] = 7 instead
ACT
D, D
D, D
PRE
ACT
D, D
D, D
PRE
0
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
Page 32 of 59
1
0
1
1
1
0
1
1
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
00
00
00
00
00
00
00
DDP 2Gb DDR3 SDRAM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Rev. 1.0 March 2009
0
0
0
0
F
F
F
F
0
0
0
0
0
0
0
0
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