ppc440spe Applied Micro Circuits Corporation (AMCC), ppc440spe Datasheet - Page 74

• Manufacturer Part Number: ppc440spe
• Description: Powerpc 440spe Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

PowerPC 440SPe Embedded Processor
DDR SDRAM Read Operation
The Read of the incoming Data from the SDRAM is done on the rising and falling edges of the differential DQS
signal. The Data must be centered to these edges for correct operation.
The PPC440SPe can delay with very fine granularity the DQS through the programming of the
MCIF0_RODC[RQFD] register field.
DDR SDRAM MemClkOut0 and Read Clock Delay
In order to accommodate timing variations introduced by the system designs using this chip, the three-stage data
path shown below is used to eliminate metastability and allow data sampling to be adjusted for minimum latency.
The data are stored in the 8 Flip Flops of the Stage 1, such that it can be transferred later within a 8X period.
Figure 9. DDR SDRAM Read Data Path
74
MemDCFdbkR
Ext FeedBack
Signals
MemDCFdbkD
Package
pins
DQ
Data
(x64)
DQS
(Diff)
Programmed
Rec
MCIF0_RQDC[RQFD]
Read DQS
Mux
Delay
Driver
MCIF0_RFDC[RFFD]
0
Feedback
Data Capture
Window
1
Coarse Delay
Fine Delay
Stage 1
FF
FF
7
DQS Falling
Edge Sync
DQS Rising
Edge Sync
DQS aligned
FBK signal
0
2
4
6
1
3
5
7
MCIF0_RDCC[RDSS]
Mux
DDR 1X Clock
D
D
DDR 1X Clock
DDR 1X Clock
FeedBack
Signal Gen
Stage 2
Stage 2 Store
Cycles
Delay
FF
FF
FF
FF
T1 T2 T3 T4
C
C
Q2_Ovs
Q2
(x64)
(x64)
+1
CAS Lat Delay
Compare
adjust
Oversampling
Fine Delay
Preliminary Data Sheet
Read FIFO
Upper
Lower
Read Start
Oversampling
Clock
Read Latency adjust circuit
MCIF0_RFDC[RFOS]
Revision 1.23 - Sept 21, 2006
PLB 1X Clock
Stage 3
FF
Q3
FF: Flip-Flop
AMCC Proprietary
PLB bus
[0:63]
PLB bus
[64:127]