ppc440spe Applied Micro Circuits Corporation (AMCC), ppc440spe Datasheet - Page 56

• Manufacturer Part Number: ppc440spe
• Description: Powerpc 440spe Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

PowerPC 440SPe Embedded Processor
Table 6. Signal Functional Description (Sheet 7 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k: to 3.3V
3. Must pull down (recommended value is 1k:)
4. If not used, must pull up (recommended value is 3k: to 3.3V)
5. If not used, must pull down (recommended value is 1k:)
6. Strapping input during reset; pull-up or pull-down required
56
HISRRst
TESTEN
TMR_CLK
JTAG Interface
TCK
TDI
TDO
TMS
TRST
Trace Interface
TrcClk
TRCBS0:2
TrcES0:4
TrcTS0:6
Tests
SCANOUT[00][07:08] [14:21] [25]
Power
PCIE0:2AV25
PCIE_PLLVDD2
PCIE_PLLVDDA
PCIE_PLLVDDB
PCIE_PLLGNDA
PCIE_PLLGNDB
PCIX0PLLG
PCIX0PLLV
Signal Name
Hardware initiated system reset with an initial SDRAM
self-refresh phase to save data in Memory.
Test Enable.
Processor timer external input clock.
Test Clock.
Test Data In.
Test Data Out.
Test Mode Select.
Test Reset. During chip power-up, this signal must be
low from the start of VDD ramp-up until at least 16
SysClk cycles after VDD is stable in order to initialize the
JTAG controller.
Trace data capture clock, runs at 1/4 the frequency of
the processor.
Trace branch execution status.
Trace Execution Status is presented every fourth
processor clock cycle.
Additional information on trace execution and branch
status.
Test scan out
Manufacturing test signals: No need for termination
2.5V supply voltage for the serial link of the PCI Express
2.5V supply voltage for the PCI Express Reference
clock Input receiver in front of the PLL
Analog 2.5V filtered supply voltage A for the PLL of the
PCI Express
Analog 2.5V filtered supply voltage B for the PLL of the
PCI Express
GNDA for the PLL of the PCI Express
GNDB for the PLL of the PCI Express
Ground for the PCI-X0 PLL
Analog 1.5V Filtered Supply voltages input for PCI-X0
A separate filter for all analog voltages is recommended.
Description
n/a
n/a
I/O
O
O
O
O
O
Preliminary Data Sheet
I
I
I
I
I
I
I
I
I
I
I
I
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
w/pull-down
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
with pull-up
with pull-up
Revision 1.23 - Sept 21, 2006
Type
n/a
n/a
Notes
AMCC Proprietary
1, 2
3
1
1
5
4