ppc440spe Applied Micro Circuits Corporation (AMCC), ppc440spe Datasheet - Page 51

• Manufacturer Part Number: ppc440spe
• Description: Powerpc 440spe Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

PowerPC 440SPe Embedded Processor
Table 6. Signal Functional Description (Sheet 2 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k: to 3.3V
3. Must pull down (recommended value is 1k:)
4. If not used, must pull up (recommended value is 3k: to 3.3V)
5. If not used, must pull down (recommended value is 1k:)
6. Strapping input during reset; pull-up or pull-down required
AMCC Proprietary
PCIX0Clk
PCIX0DevSel
PCIX0ECC5:2
PCIX0Frame
PCIX0Gnt0
PCIX0Gnt1:3
PCIX0IDSel
PCIX0INTA
PCIX0IRDY
PCIX0M66En
PCIX0Par/PCIX0ECC0
PCIX0Par64/PCIX0ECC7
PCIX0PErr
PCIX0Req0
PCIX0Req1:3
Signal Name
Input PCI & PCI-X Clock.
Note:
Indicates the driving device has decoded its address as
the target of the current access.
ECC check bits 5–2. All ECC bits are valid only for PCIX
DDR mode 2.
Note:
Driven by the current master to indicate beginning and
duration of an access.
Indicates that the specified agent is granted access to
the PCI-X bus. When Arbitration is internal to the
PPC440SPe, all GRANTS Gnt0:3 are outputs. When
arbitration is external, only Gnt 0 is used as an Input.
Used as a chip select during configuration read and
write transactions. If the PCI-X is a Host, during
Configuration the ISDSEL is an Output that duplicates
the AD17. The ISDSEL is always 3.3V even in Mode 2
DDR
Level sensitive PCI interrupt.
Indicates initiating agent’s ability to complete the current
data phase of the transaction.
Capable of 66MHz operation.
Even parity indicator or ECC0.
Normally used to indicate even parity across
PCIAD31:00 and BE3:0.
Used as ECC0 for PCIX0 mode 2.
Even parity indicator or ECC7.
Normally used to indicate even parity across
PCIXAD63:32 and BE7:4 for PCIX0
or
Used as ECC7 for PCIX0 mode 2.
Reports data parity errors during all PCI transactions
except a Special Cycle.
An indication to the PCI-X arbiter that the specified
agent wishes to use the bus.
When Arbitration is internal to the PPC440SPe, all
REQS Req0:3 are Inputs. When arbitration is external,
only Req 0 is used as an output.
If the PCI-X interface is not being used, drive this
pin with a 3.3V clock signal at a frequency
between 1 and 66MHz
See PCIXPar for ECC0.
See PCIXAck64 for ECC1.
See PCIXReq64 for ECC6.
See PCIXPar64 for ECC7.
Description
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
Preliminary Data Sheet
I
I
I
1.5V PCI for
1.5V PCI for
1.5V PCI for
1.5V PCI for
3.3V PCI or
3.3V PCI or
3.3V PCI or
3.3V PCI or
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
Revision 1.23 - Sept 21, 2006
mode 2
mode 2
mode 2
mode 2
Type
Notes
4
4
4
5
4
4
4
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