ppc440spe Applied Micro Circuits Corporation (AMCC), ppc440spe Datasheet - Page 10

• Manufacturer Part Number: ppc440spe
• Description: Powerpc 440spe Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

PowerPC 440SPe Embedded Processor
On-Chip SRAM/L2 Cache
Features include:
PCI Express
Features include:
10
• OPB
• DCR
• Four banks of 64KB each for a total of 256KB
• Configurable as either L2 cache or SRAM
• Memory cycles supported:
• Sustainable 2.6GB/s peak bandwidth at 166MHz
• Use as an L2 cache improves processor performance and reduces the PLB load
• Use as Ethernet packet store allows Ethernet packets to be held for processing by the Ethernet core
• Three independent PCI Express interfaces
• Compliant with PCI Express base specification 1.0a
• Each PCI Express port can be End Point or Root Complex. (Upstream & Downstream)
• PCI-Express to PCI-Express opaque (Non-Transparent) bridge
• Power Management
• Supports one virtual channel (VC0) no Traffic Class (TC) filtering
• Maximum Payload block size 512 Bytes
• Supports up to 1024 byte maximum Read request size
• Requests supported:
– 166MHz, maximum 5.2GB/s (simultaneous read and write)
– Processor vs Bus clock ratios of N:1 and N:2
– Dynamic bus sizing: 32, 16, and 8-bit data path
– 32-bit address
– 83.33MHz, maximum 333MB/s
– Register control bus
– 32-bit data path
– 10-bit address
– Single beat read and write, 1 to 16 bytes
– Quadword Read and Write burst for 12-bit master
– Guarded memory accesses on 4KB boundaries
– Cache coherency maintained by a hardware snoop mechanism on the Low Latency (LL) PLB or by
– Data Array and Tag Array parity
– Unified data and instruction cache
– Four-way set associative
– 36-bit addressing
– Full LRU replacement algorithm
– Write through, look aside
– One 8 lanes
– Two 4 lanes
– 2.5 GB/sec full duplex per lane
– Applications compliant with MSI rules are limited to one End Point port per PPC440SPe
– up to 4 posted outbound Write requests (memory and messages)
– up to 4 posted inbound Write requests
– up to 4 outbound Read requests outstanding on PCI Express
– up to 4 inbound Read requests outstanding on PCI Express
– Outbound I/O request as a PCI Express Root Port
– Inbound I/O request as a PCI Express End Point
software
Preliminary Data Sheet
Revision 1.23 - Sept 21, 2006
AMCC Proprietary