ppc440spe Applied Micro Circuits Corporation (AMCC), ppc440spe Datasheet - Page 72

• Manufacturer Part Number: ppc440spe
• Description: Powerpc 440spe Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

PowerPC 440SPe Embedded Processor
DDR SDRAM Write Operation
The following timing chart shows the relationship between the signals involved in a DDR write operation.
Figure 8. DDR SDRAM Write Cycle Timing
DDR SDRAM Read and Write I/O Timing—T
Note 1: Clock speed is 333 MHz. T
Note 2: Memory clock signal is shifted by 90q from the internal clock.
Table 17. DDR SDRAM Read and Write I/O Timing—T
72
MemAddr00:12
BA0:1
BankSel0:3
ClkEn0:3
CAS
RAS
WE
Signal Name
T
T
T
T
T
MemClkOut
SA
HA
SD
HD
DS
Addr/Cmd
Minimum
MemData
T SA (ns)
= Setup time for address and command signals to MemClkOut
= Hold time for address and command signals from MemClkOut
= Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)
= Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)
= Delay from rising/falling edge of clock to the rising/falling edge of DQS
PLB Clk
1.32
1.15
1.12
1.29
1.24
1.29
1.35
DQS
SA
and T
T
Minimum
SA
T HA (ns)
1.49
1.52
1.45
1.14
1.48
1.43
1.2
HA
T
are referenced to MemClkOut.
HA
T
DS
SA
SA
and T
T
SD
and T
T
HD
HA
HA
T
SD
T
HD
Preliminary Data Sheet
Revision 1.23 - Sept 21, 2006
AMCC Proprietary