mt18vddt12872phg-335 Micron Semiconductor Products, mt18vddt12872phg-335 Datasheet

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... Address Table Refresh Count Row Addressing Device Bank Addressing Base Device Configuration Column Addressing Module Rank Addressing pdf: 09005aef81697898/source: 09005aef8169786e DD18C128x72PHG.fm - Rev. A 10/04 EN PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 1GB (x72, ECC, PLL) 200-PIN DDR SDRAM SODIMM MT18VDDT12872PH(I) – ...

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... MT18VDDT12872PHY-262__ MT18VDDT12872PHG-26A__ MT18VDDT12872PHY-26A__ MT18VDDT12872PHG-265__ MT18VDDT12872PHY-265__ NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT18VDDT12872PHG-335A1. pdf: 09005aef81697898/source: 09005aef8169786e DD18C128x72PHG.fm - Rev. A 10/04 EN 200-PIN DDR SDRAM SODIMM MODULE CONFIGURATION BANDWIDTH ...

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... 193 SDA 44 DD DQ41 195 SCL 46 DQS5 197 V 48 DDSPD V 199 Figure 2: Module Layout Back View PIN 199 PIN 200 Indicates pin 1GB (x72, ECC, PLL) Pin Assignment (200-Pin SODIMM Back 102 A8 REF ...

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Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information PIN NUMBERS SYMBOL 118, 119, 120 WE#, CAS#, RAS# 35, 37 CK0, CK0# 95, 96 CKE0, CKE1 121, ...

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... Input/ Data I/Os: Data bus. Output SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. SDA Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to ...

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... WE# NOTE: 1. All resistor values are 22 unless otherwise specified. 2. 'b' = bottom portion of stacked SDRAM, 't' = top portion of stacked SDRAM. 3. Per industry standard, Micron modules utilize various component speed grades, as referenced in the module part numbering guide at www.micron.com/numberguide. pdf: 09005aef81697898/source: 09005aef8169786e DD18C128x72PHG.fm - Rev. A 10/04 EN 200-PIN DDR SDRAM SODIMM ...

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... SSTL_2, Class II compatible. information regarding DDR SDRAM operation, refer to the 512Mb DDR SDRAM data sheets. PLL Operation A phase-lock loop (PLL) on the module is used to redrive the differential clock signals CK and CK# to the DDR SDRAM devices to minimize system clock load- ing. ...

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Vio- lating either of these requirements will result in unspecified operation. Mode register bits A0–A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4–A6 specify the CAS latency, and ...

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Table 6: Burst Definition Table ORDER OF ACCESSES WITHIN STARTING BURST COLUMN TYPE = LENGTH ADDRESS SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1 ...

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All other combinations of values for A7–A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future ver- sions may result. Extended Mode Register The extended ...

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Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH ...

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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...

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... RC (MIN); and control inputs change only during Active READ, or WRITE commands NOTE Value calculated as one module rank in this operating condition, and all other module ranks Value calculated reflects all module ranks in this operating condition. pdf: 09005aef81697898/source: 09005aef8169786e DD18C128x72PHG.fm - Rev. A 10/04 EN ...

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Table 13: Capacitance Note: 11; notes appear on pages 16–19 PARAMETER Input/Output Capacitance: DQ, DQS, DM Input Capacitance: Command and Address Input Capacitance: S# Input Capacitance: CK, CK# Input Capacitance: CKE Table 14: Electrical Characteristics and Recommended AC Operating Conditions ...

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Table 14: Electrical Characteristics and Recommended AC Operating Conditions (Continued) DDR SDRAM components only; notes appear on pages 16–19 AC CHARACTERISTICS PARAMETER DQ-DQS hold, DQS to first non- valid, per access Data Hold Skew Factor ACTIVE to ...

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Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...

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DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving t t other specifications CK/2 QHS). The data valid window ...

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Any positive glitch must be less than 1/3 of the clock and not more than +300mV or 2.9V, which- ever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either - ...

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... DD18C128x72PHG.fm - Rev. A 10/04 EN 200-PIN DDR SDRAM SODIMM 45. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 46. When an input signal is HIGH or LOW defined as a steady state logic HIGH or LOW. ...

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Initialization To ensure device operation the DRAM must be ini- tialized as described below: 1. Simultaneously apply power Apply V and then V power. REF TT 3. Assert and hold CKE at a LVCMOS logic low. 4. ...

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... The timing and switching specifications for the PLL listed above are critical for proper operation of the DDR SDRAM Registered DIMMs. These are meant subset of the parameters for the specific device used on the module. Detailed information for this PLL is available in JEDEC Standard JESD82. ...

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... NOTE: 1. Micron Technology, Inc. recommends a minimum air flow of 1 meter/second (~197 LFM) across all modules. 2. The component case temperature measurements shown above were obtained experimentally. The typical system to be used for experimental purposes is a dual-processor 600 MHz work station, fully loaded, with four comparable registered memory modules ...

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SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 12, Data Validity, and Figure ...

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Table 16: EEPROM Device Select Code Most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 17: EEPROM Operating Modes MODE RW BIT Current Address Read 1 Random Address Read ...

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Table 18: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...

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... Fundamental Memory Type 3 Number of Rows Addresses on Assembly 4 Number of Column Addresses on Assembly 5 Number of Physical Ranks on DIMM 6 Module Data With 7 Module Data With (Continued) 8 Moduel Voltage Interface Levels 9 t SDRAM Cycle Time, ( CK), CAS Latency = 2.5 (see note 1) 10 SDRAM Access from Clock,( 11 Module Configuration Type ...

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... The value of RP, RCD, and RAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR SDRAM device specification is 15ns. pdf: 09005aef81697898/source: 09005aef8169786e DD18C128x72PHG.fm - Rev. A 10/04 EN 200-PIN DDR SDRAM SODIMM ENTRY (VERSION) 0.8ns (-335) ...

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Figure 16: 200-Pin SODIMM Dimensions 0.079 (2.00) R (2X) U1 0.071 (1.80) (2X) 0.236 (6.00) 0.096 (2.44) 0.079 (2.00) 0.039 (0.99) U6 PIN 200 NOTE: All dimensions are in inches (millimeters); Data Sheet Designation Released (No Mark): This data sheet ...