mt18htf25672pdz Micron Semiconductor Products, mt18htf25672pdz Datasheet - Page 7

• Manufacturer Part Number: mt18htf25672pdz
• Description: 2gb X72, Ecc, Dr 240-pin Ddr2 Sdram Rdimm
• Manufacturer: Micron Semiconductor Products

General Description
Register and PLL EEPROM Operation
Parity Operations
Serial Presence-Detect EEPROM Operation
PDF: 09005aef83d3d893/Source: 09005aef83d3d8c1
htf18c256x72pdz.fm - Rev. A 11/09 EN
The MT18HTF25672PDZ DDR2 SDRAM module is a high-speed, CMOS, dynamic ran-
dom-access 2GB memory module organized in a x72 configuration. This DDR2 SDRAM
module use internally configured 8-bank 1Gb DDR2 SDRAM devices.
DDR2 SDRAM modules use double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 4n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bit-
wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding
n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM
device during READs and by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-
mands are registered at every positive edge of CK. Input data is registered on both edges
of DQS, and output data is referenced to both edges of DQS, as well as to both edges of
CK.
DDR2 SDRAM modules operate in registered mode, where the command/address input
signals are latched in the registers on the rising clock edge and sent to the DDR2 SDRAM
devices on the following rising clock edge (data access is delayed by one clock cycle). A
phase-lock loop (PLL) on the module receives and redrives the differential clock signals
(CK, CK#) to the DDR2 SDRAM devices. The register(s) and PLL reduce address, com-
mand, control, and clock signal loading by isolating DRAM from the system controller.
PLL clock timing is defined by JEDEC specifications and ensured by use of the JEDEC
clock reference board. Registered mode will add one clock cycle to CL.
The registering clock driver can accept a parity bit from the system’s memory controller,
providing even parity for the control, command, and address bus. Parity errors are
flagged on the Err_Out pin. Systems not using parity are expected to function without
issue if Par_In and Err_Out are left as no connects to the system.
DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module
type and various SDRAM organizations and timing parameters. The remaining 128 bytes
of storage are available for use by the customer. System READ/WRITE operations
between the master (system logic) and the slave EEPROM device occur via a standard
I
which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is connected
to V
2
C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA[2:0],
SS
, permanently disabling hardware write protection.
2GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
General Description
©2009 Micron Technology, Inc. All rights reserved.