mt18htf25672pdz Micron Semiconductor Products, mt18htf25672pdz Datasheet - Page 13

• Manufacturer Part Number: mt18htf25672pdz
• Description: 2gb X72, Ecc, Dr 240-pin Ddr2 Sdram Rdimm
• Manufacturer: Micron Semiconductor Products

Serial Presence-Detect
Table 12:
Table 13:
Serial Presence-Detect Data
PDF: 09005aef83d3d893/Source: 09005aef83d3d8c1
htf18c256x72pdz.fm - Rev. A 11/09 EN
Parameter/Condition
Parameter/Condition
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output low voltage: I
Input leakage current: V
Output leakage current: V
Standby current
Power supply current, READ: SCL clock frequency = 100 kHz
Power supply current, WRITE: SCL clock frequency = 100 kHz
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to V
Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to V
OUT
Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1
IN
= 3mA
OUT
= GND to V
For the latest serial presence-detect data, refer to Micron's SPD page:
www.micron.com/SPD.
2. This parameter is sampled.
3. For a restart condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
= GND to V
and the falling or rising edge of SDA.
write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the
WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-
up resistance, and the EEPROM does not respond to its slave address.
DD
SS
SS
DD
; V
; V
DDSPD
DDSPD
= +1.7V to +3.6V
= +1.7V to +3.6V
2GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
13
t
Symbol
t
t
t
t
HD:DAT
Symbol
HD:STA
SU:DAT
t
SU:STA
SU:STO
t
V
t
t
WRC) is the time from a valid stop condition of a
t
HIGH
LOW
f
WRC
t
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BUF
I
DDSPD
SCL
AA
DH
V
I
CCW
t
V
t
V
I
t
I
CCR
I
F
R
LO
SB
I
OL
LI
IH
IL
V
Min
200
100
0.2
1.3
0.6
0.6
1.3
0.6
0.6
DDSPD
0
–
–
–
–
–
Min
–0.6
0.10
0.05
1.7
1.6
0.4
2
–
× 0.7
Serial Presence-Detect
Max
300
400
0.9
0.3
50
10
©2009 Micron Technology, Inc. All rights reserved.
–
–
–
–
–
–
–
–
–
V
V
DDSPD
DDSPD
Max
3.6
0.4
3
3
4
1
3
Units
+ 0.5
× 0.3
kHz
ms
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
ns
µs
µs
Units
Notes
mA
mA
µA
µA
µA
V
V
V
V
1
2
2
3
4