lrs1331 Sharp Microelectronics of the Americas, lrs1331 Datasheet - Page 20

• Manufacturer Part Number: lrs1331
• Description: Stacked Chip Flash Memory Sram
• Manufacturer: Sharp Microelectronics of the Americas

LRS1331
20
NOTES:
1. A write occurs during the overlap of a LOW S-CE
2. t
3. t
4. t
5. t
6. During this period, DQ pins are in the output state, therefore the input signals of
7. If S-CE
8. If S-CE
and S-WE going LOW. A write ends at the earliest transition among S-CE
S-CE
write to the end of write.
A write begins at the latest transition among S-CE
opposite phase to the outputs must not be applied.
of write.
write ends as S-CE
after S-WE going LOW, the outputs remain in HIGH impedance state.
S-WE going HIGH, the outputs remain in HIGH impedance state.
CW
BW
AS
WR
is measured from the address valid to the beginning of write.
is measured from the time of going LOW S-UB or LOW S-LB to the end of write.
is measured from the later of S-CE
is measured from the end of write to the address change. t
2
S-UB, S-LB
ADDRESS
going LOW and S-WE going HIGH. t
1
1
goes LOW or S-CE
goes HIGH or S-CE
S-CE
S-CE
S-WE
D
OUT
D
IN
1
2
1
going HIGH, S-CE
2
2
Figure 9. Write Cycle Timing Diagram (S-WE Controlled)
goes HIGH simultaneously with S-WE going LOW or
goes LOW simultaneously with S-WE going HIGH or
1
2
going LOW or S-CE
going LOW or S-WE going HIGH.
(NOTE 4)
WP
t
AS
is measured from the beginning of
1
1
, a HIGH S-CE
going LOW, S-CE
2
going HIGH to the end
WR
(NOTE 7)
2
t
t
AW
and a LOW S-WE,
WZ
applied in case a
2
(NOTE 6)
going HIGH
t
WC
(NOTE 2)
1
(NOTE 3)
going HIGH,
t
t
(NOTE 1)
CW
BW
t
WP
Stacked Chip (16M Flash & 4M SRAM)
t
DW
Data Valid
(NOTE 5)
t
WR
t
WR
(NOTE 8)
t
DH
t
OW
Data Sheet
1331-9