am49lv128bm Meet Spansion Inc., am49lv128bm Datasheet - Page 62

• Manufacturer Part Number: am49lv128bm
• Description: Stacked Multi-chip Package Mcp ,128 Megabit 8 M ? 16-bit ,uniform Sector Flash Memory And 32 Mbit 2 M ? 16-bit Pseudo-static Ram With Page Mode Featuring Mirrorbit Technology,supplemental Datasheet
• Manufacturer: Meet Spansion Inc.

PSRAM AC CHARACTERISTICS
Write Operation
Notes:
1. Maximum value is applicable if CE1# is kept at Low
2. Minimum value must be equal or greater than the sum of
3. Write pulse is defined from High to Low transition of CE1#,
4. Applicable for byte mask only. Byte mask setup time is
5. Applicable for byte mask only. Byte mask hold time is
6. Write recovery is defined from Low to High transition of
60
without any address change.
write pulse (t
T
WE#, or LB#/UB#, whichever occurs last.
defined to the High to Low transition of CE1# or WE#
whichever occurs last.
defined from the Low to High transition of CE1# or WE#
whichever occurs first.
CE1#, WE#, or LB#/UB#, whichever occurs first.
WR
WE#/UB#/LB# High to OE# Low Setup Time for Read (Note 10)
or t
OE# High to CE1# Low Setup Time for Write (Note 7)
OE# High to Address Setup Time for Write (Note 8)
BR
).
CW
Address Hold Time for Write End (Note 3)
LB#/UB# Byte Mask Setup Time (Note 4)
LB#/UB# Byte Mask Hold Time (Note 5)
LB#/UB# Write Recovery Time (Note 6)
, T
LB#/UB# Write Pulse Width (Note 3)
CE1# Write Recovery Time (Note 6)
WE# Write Recovery Time (Note 6)
LB# and UB# Write Pulse Overlap
CE1# Write Pulse Width (Note 3)
WE# Write Pulse Width (Note 3)
WP
Write Cycle Time (Notes 1, 2)
Address Setup Time (Note 3)
, T
CE1# High Pulse Width
BW
Data Setup Time
) and write recovery time (t
Data Hold Time
Parameter
Am49LV128BM
WCR
,
7. If OE# is Low after minimum t
8. If OE# is Low after new address input, read cycle is
9. Absolute minimum values and defined at minimum V
10. If the actual value of t
other words, OE# must be brought to High within 5 ns after
CE1# is brought to Low. Once read cycle is initiated, new
write pulse should be input after minimum t
initiated. In other words, OE# must be brought to High at
the same time or before new address valid. Once read
cycle is initiated, new write pulse should be input after
minimum t
level.
minimum values, the actual t
become longer by the amount of subtracting the actual
value from the specified minimum value.
Symbol
t
t
t
t
WHOL
RC
OHCL
t
t
t
WRC
t
BWO
t
t
t
t
t
t
t
t
OES
t
t
WC
CW
WR
WP
BW
AS
BS
BH
BR
DS
DH
CP
AH
is met and data bus is in High-Z
WHOL
Min.
7.5
is shorter than the specified
65
40
40
40
12
12
12
12
30
12
-5
-5
-5
0
0
0
0
AA
OHCL
Value
of following Read may
, read cycle is initiated. In
Max.
1000
1000
1000
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
June 17, 2004
RC
is met
Unit
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IH