s71ns128jc0 Advanced Micro Devices, s71ns128jc0 Datasheet - Page 83

• Manufacturer Part Number: s71ns128jc0
• Description: Stacked Multi-chip Product Mcp 128 Megabit 8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Multi-plexed Flash Memory With 64megabit 4m X 16-bit Cellularram
• Manufacturer: Advanced Micro Devices

24.4 Refresh Configuration Register
March 17, 2005 S71NS-J-00_A0
All must be set to "0"
RCR[19]
0
1
Reserved
21–20
RCR[7]
0
1
A[21:20]
Register Select
Select RCR
Select BCR
A d v a n c e
RCR[6]
1
0
0
1
Register
Select
Page Mode Enable/Disable
Page Mode Disabled (default)
Page Mode Enable
19
RCR[5]
A19
Table 24.5 64Mb Address Patterns for PAR (RCR[4] = 1)
All must be set to "0"
1
0
1
0
Table 24.4 Refresh Configuration Register Mapping
Reserved
18–8
Maximum Case Temp
+85ºC (default)
+70ºC
+45ºC
+15ºC
A[18:8]
I n f o r m a t i o n
CellularRAM Type 2
Page
7
A7
TCR
6
A6
5
A5
RCR[4]
DPD
0
1
4
A4
Must be set to "0"
Reserved
Deep Power-Down
DPD Enable
DPD Disable (default)
3
RCR[2]
A3
0
0
0
0
1
1
1
1
RCR[1] RCR[0]
0
1
1
1
1
0
0
0
2
A2
PAR
1
A1
0
1
0
1
0
1
1
0
0
A0
Refresh Coverage
Full array (default)
Bottom 1/2 array
Bottom 1/4 array
Bottom 1/8 array
None of array
Top 1/2 array
Top 1/4 array
Top 3/4 array
Address Bus
Read Configuration
Register
81