s71ns128jc0 Advanced Micro Devices, s71ns128jc0 Datasheet - Page 79

• Manufacturer Part Number: s71ns128jc0
• Description: Stacked Multi-chip Product Mcp 128 Megabit 8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Multi-plexed Flash Memory With 64megabit 4m X 16-bit Cellularram
• Manufacturer: Advanced Micro Devices

24.3 Bus Configuration Register
March 17, 2005 S71NS-J-00_A0
All must be set to "0"
Reserved
BCR[19]
A[21:20]
21–20
0
1
A d v a n c e
Register
BCR[15]
Select
0
1
19
Select RCR
Select BCR
A19
BCR[13]
Must be set to "0"
0
0
0
0
1
1
1
1
Reserved
A[18:16]
18–16
Synchronous burst access mode
Asynchronous access mode (default)
BCR[10]
BCR[12] BCR[11]
Register Select
0
1
0
0
1
1
0
0
1
1
Operating
Table 24.1 Bus Configuration Register Definition
BCR[8]
Mode
Operation Mode
0
1
15
A15
Active LOW
Active HIGH (default)
0
1
0
1
0
1
0
1
Must be set to "0"
Reserved
I n f o r m a t i o n
Asserted one data cycle before delay (default)
Asserted during delay
Code 0–Reserved
Code 1–Reserved
Code 2
Code 3 (Default)
Code 4–Reserved
Code 5–Reserved
Code 6–Reserved
Code 7–Reserved
14
Latency Counter
A14
WAIT Polarity
CellularRAM Type 2
A13
13 12 11
Counter
Latency
WAIT Configuration
A12A11 A10
Polarity
WAIT
10
Must be set to "0"
Reserved
9
A9
Configuration (WC)
WAIT
8
A8
BCR[6]
0
1
Must be set to "0"
Reserved
BCR[5]
Rising edge (default)
Not supported
7
A7
0
1
BCR[3]
Configuration (CC)
0
1
Full Drive (default)
1/4 Drive
Clock Configuration
Output Impedance
Clock
BCR[2]
6
A6
0
0
0
1
Burst wraps within the burst length
Burst no wrap (default)
BCR[1] BCR[0]
0
1
1
1
Impedance
Output
Burst Wrap (Note 1)
5
A5
1
0
1
1
Must be set to "0"
Reserved
4 words
8 words
16 words
Continuous burst (default)
A4
4
Burst Length (Note 1)
Wrap (BW)*
Burst
A3
3
Length (BL)*
2
A2 A1 A0
Burst
1
0
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