s71ns128jc0 Advanced Micro Devices, s71ns128jc0 Datasheet - Page 61

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s71ns128jc0

Manufacturer Part Number
s71ns128jc0
Description
Stacked Multi-chip Product Mcp 128 Megabit 8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Multi-plexed Flash Memory With 64megabit 4m X 16-bit Cellularram
Manufacturer
Advanced Micro Devices
Datasheet
March 17, 2005 S71NS-J-00_A0
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Address (hex)
Address (hex)
A/DQ15
A/DQ15
A/DQ0
A/DQ0
AVD#
AVD#
OE#,
RDY
CLK
CE#
OE#
CLK
CE#
A d v a n c e
V
V
V
V
Figure 17.11 8-, 16-, and 32-Word Linear Burst Address Wrap Around
IH
IH
IL
IL
V
V
V
V
IH
IH
IL
IL
(stays high)
(stays low)
3C
V
39
IL
Initial Access
C60
D60
00003Fh: 00007Fh, 0000BFh, etc. Address 000000h is also a boundary crossing.
3D
(stays low)
Figure 17.12 Latency with Boundary Crossing
C61
39
I n f o r m a t i o n
S71NS128JC0 Based MCP
Address boundary occurs every 64 words, beginning at address
D61
3E
D0
C62
3A
D62
3F
D1
C63
3B
D2
latency
C63
3C
D63
Address wraps back to beginning of address group.
t
RACC
D3
C63
3D
40
D4
C64
3E
D64
41
C65
D5
3F
42
D65
C66
D6
38
43
D66
C67
D7
D67
59

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