m36l0t8060b1 STMicroelectronics, m36l0t8060b1 Datasheet - Page 11
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m36l0t8060b1
Manufacturer Part Number
m36l0t8060b1
Description
256 Mbit 16 Mb , Multiple Bank, Multilevel, Burst Flash Memory And 64 Mbit Psram, 1.8 V Core, 3 V I/o Supply, Multichip Package
Manufacturer
STMicroelectronics
Datasheet
1.M36L0T8060B1.pdf
(22 pages)
M36L0T8060T1, M36L0T8060B1
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
PSRAM Chip Enable (E2
The Chip Enable, E2
standby) when it is driven Low. Deep power-down mode is the lowest power mode.
It is not allowed to set E
PSRAM Output Enable (G
The Output Enable, G
cycles to be achieved with the common I/O data bus.
PSRAM Write Enable (W
The Write Enable, W
PSRAM Upper Byte Enable (UB
The Upper Byte Enable, UB
DQ15) to or from the upper part of the selected address during a write or read operation.
PSRAM Lower Byte Enable (LB
The Lower Byte Enable, LB
DQ7) to or from the lower part of the selected address during a write or read operation.
Flash V
V
power supply for all Flash memory operations (read, program, and erase).
PSRAM V
The V
for driving the refresh logic, even when the device is not being accessed.
Flash V
V
powered independently of the Flash memory core power supply, V
DDF
DDQF
provides the power supply to the internal core of the Flash memory. It is the main
CCP
provides the power supply for the Flash I/O pins. This allows all outputs to be
supply voltage supplies the power for all PSRAM operations (read, write, etc.) and
DDF
DDQF
CCP
supply voltage
supply voltage
supply voltage
P
P
, puts the device in power-down mode (deep power-down, PAR and
, controls the bus write operation of the PSRAM’s command interface.
P
, provides a high speed tri-state control, allowing fast read/write
F
to V
P
P
, gates the data on the lower byte data inputs/outputs (DQ0-
, gates the data on the upper byte data inputs/outputs (DQ8-
IL
, E1
P
P
P
to V
)
)
P
)
IL
and E2
P
P
)
)
P
to V
IH
at the same time.
DDF
.
Signal descriptions
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