xe1205 Semtech Corporation, xe1205 Datasheet - Page 9
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xe1205
Manufacturer Part Number
xe1205
Description
Low-power, High Link Budget Integrated Uhf Transceiver
Manufacturer
Semtech Corporation
Datasheet
1.XE1205.pdf
(48 pages)
- Current page: 9 of 48
- Download datasheet (764Kb)
If the bit synchronizer is disabled, the DCLK output is held low and the raw demodulator output appears at DATA.
.
5.2.3.1
The demodulator section comprises FSK demodulator, bit synchronizer, and Pattern Recognition blocks.
Data from the FSK baseband limited signals I_lim and Q_lim is first demodulated before passing to the bit synchronizer.
If the end-user application requires direct access to the output of the demodulator, then the RXParam_Disable_bitsync
bit must be set high. In this case the demodulator output is directly connected to the DATA pin and the IRQ_1 pin
(DCLK) is set to low.
For best operation of the demodulator it is recommended the modulation index
condition:
where Df is the frequency deviation and BR the bit rate.
© Semtech 2007
b
=
Q_lim
I_lim
2
BR
D
f
³
2
Demodulator in continuous mode
DEMODULATOR
FSK
RXParam_RSSI
data
RSSI
RXParam_Disable_bitsync
SYNCHRONIZER
Figure 2: Receiver chain in continuous mode
BIT
data
dclk
9
RSSI_irq
RXParam_Pattern
MATCHING
PATTERN
1
0
pattern
of the input signal meets the following
IRQParam_Rx_irq_0(1:0)
IRQ_1(DCLK)
XE1205
www.semtech.com
IRQ_0
DATA
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