xe1205 Semtech Corporation, xe1205 Datasheet - Page 14

• Manufacturer Part Number: xe1205
• Description: Low-power, High Link Budget Integrated Uhf Transceiver
• Manufacturer: Semtech Corporation

written to
automatically set to
frequency error is too high to be automatically cancelled.
5.2.4
The DATA pin is bi-directional by default, and is used in both transmit and receive modes. In receive mode, DATA
represents demodulated received data. In transmit mode baseband data is applied to this pin.
Some applications may require a separate input and output for transmitted and received data respectively. In this case
the MCParam_Data_unidir configuration register bit must be set to
output for received data, and NSS_DATA is used as the input.
5.2.5
In this mode, the output of the bit synchronizer, i.e. the demodulated and resynchronized signal and the clock signal
DCLK are not sent directly to the output pins DATA and IRQ_1 (DCLK). These signals are used to store the
demodulated signal by packet of 8 bits in a 16 bytes FIFO. The following figure shows the receiver chain in this mode.
© Semtech 2007
.
Q_lim
I_lim
DATA pin in bidirectional or unidirectional mode (continuous mode only)
Receiver in buffered mode
DEMODULATOR
.Refer to previous chapter to guarantee proper behaviour of the FEI. RXParam_AFC_OK status register is
FSK
/RXParam_Disable_bitsync
when AFC is completed. RXParam_AFC_overflow will be automatically set to
RXParam_RSSI
RSSI
SYNCHRONIZER
=
BIT
Figure 8: Receiver chain in buffered mode
RSSI_irq
data
dclk
14
Shift reg
FIFO
8
RXParam_Pattern
MATCHING
PATTERN
8
=
. The DATA pin is then set permanently to an
regspidata
DATA
SPI
Fifofull
write_byte
/fifoempty
pattern
XE1205
NSS_DATA
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MOSI
MISO
SCK
in case the
IRQ_0
IRQ_1