xe1205 Semtech Corporation, xe1205 Datasheet - Page 15

• Manufacturer Part Number: xe1205
• Description: Low-power, High Link Budget Integrated Uhf Transceiver
• Manufacturer: Semtech Corporation

The FSK demodulator, bit synchronizer and pattern matching block work as described in section 5.2.2 but they are used
with two additional blocks, FIFO and SPI.
When the chip is in receive mode and the MCParam_Buffered_mode bit is set to high then all the blocks described
above are automatically enabled. In a normal communication frame the data stream comprises a 24 bit preamble,
pattern (refer to section 5.2.3.3) and the data. Upon receipt of a recognized pattern, the receiver recognizes the start of a
frame, strips off the preamble and pattern, then fills the FIFO with payload data to the microcontroller. This automated
data recovery reduces the overhead for the host controller.
The IRQParam_Start_fill bit determines how the FIFO is filled:
If IRQParam_Start_fill is low, data only fills the FIFO subject to a correct pattern match. Data is shifted into the pattern
recognition block which continuously compares the received data with the contents of the Reg_pattern(31:0)
configuration register. If a match occurs a start sequence is detected, and the internal output of the pattern matching
block is asserted for one bit length and the IRQParam_Start_detect bit is also asserted. This internal signal may be
mapped to the IRQ_0 output using interrupt signal mapping (please refer to section 5.2.2). Once a pattern match has
occurred, the pattern recognition block will remain inactive until IRQParam_Start_detect is re-asserted.
If IRQParam_Start_fill is high, FIFO filling is initiated by asserting IRQParam_Start_detect.
Once sixteen bytes have been written to the FIFO the IRQParam_Fifofull signal is asserted. Data should then normally
be read out. If no action is taken the FIFO will overflow and subsequent data will be lost. If this occurs the
IRQParam_Fifooverrun bit is set. The IRQParam_Fifofull signal can be mapped to pin IRQ_1 as an interrupt for a
microcontroller if IRQParam_RX_irq_1 is set to 01 (please refer to section 5.2.2).
To recover from an overflow situation a
FIFO, resets all FIFO status flags and re-initiates pattern matching (only when an overrun has occurred).
In order to clear the FIFO in reception, a
Pattern matching can also be re-initiated during a FIFO filling sequence by writing a
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0
/fifoempty
data
pattern
fifofull
Fifooverrun
(flag)
write_byte
noisy data
preamble
c
pattern
b0
Figure 9: Start detection and FIFO filling
must be written to IRQParam_Fifooverrun; this clears the contents of the
should be written in IRQParam_start_detect (bit 6 add 6).
b0
b1
b2
b1
b3
b2
b4
b3
15
b5
b4
b6
b5
b7
b6
b8
b7
b9
b8
b9
b10
to IRQParam_Start_detect.
b10
b11
b11
b12 b13
b12
XE1205
b13
b14 b15
b14
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b15
b16