xe1205 Semtech Corporation, xe1205 Datasheet - Page 30

• Manufacturer Part Number: xe1205
• Description: Low-power, High Link Budget Integrated Uhf Transceiver
• Manufacturer: Semtech Corporation

Name
Freq_lo(15:8)
Freq_lo(7:0)
7.2.3
The detailed description of the IRQParam register is given in Table 18.
Name
Rx_irq_0(1:0)
Rx_irq_1(1:0)
Tx_irq_1
Fifofull
/fifoempty
Fifooverrun
Start_fill
Start_detect
© Semtech 2007
(6) When frequency band is set to 863-870MHz, 869MHz should be considered as the middle of the range.
(7) When frequency band is set to 433-435MHz, MSB is bit 14 and bit 15 is not used.
IRQParam configuration register (IRQ parameters)
(7)
Bits
7-0
7-0
Bits
7-6
5-4
3
2
1
0
7
6
Address RW
3
4
Address RW
5
5
5
5
5
5
6
6
r/w
r/w
r/w
r/w
r/w
r
r
r/w/c
r/w
r/w/c
Table 17: MCParam configuration register
Description
LO frequency in 2 s complement:
00 0 -> Flo = middle of the range
0X X-> Flo = higher than the middle of the range
1X X-> Flo = lower than the middle of the range
Example: 00 001 -> Flo = middle of the range + FSTEP
Description
Select IRQ_0 source in Rx mode:
If Buffered_mode = 0
00 -> IRQ_0 mapped to Pattern signal
01 -> IRQ_0 mapped to RSSI_irq signal
10 -> IRQ_0 mapped to Pattern signal
11 -> IRQ_0 mapped to Pattern signal
if Buffered_mode = 1
00 -> IRQ_0 set to
01 -> IRQ_0 mapped to Write_byte signal
10 -> IRQ_0 mapped to /fifoempty signal
11 -> IRQ_0 mapped to Pattern signal
Select IRQ_1 source in Rx mode
If Buffered_mode = 0
00 -> IRQ_1 mapped to DCLK signal
01 -> IRQ_1 mapped to DCLK signal
10 -> IRQ_1 mapped to DCLK signal
11 -> IRQ_1 mapped to DCLK signal
if Buffered_mode = 1
00 -> IRQ_1 set to
01 -> IRQ_1 mapped to Fifofull signal
10 -> IRQ_1 mapped to RSSI_irq signal
11 -> IRQ_1 mapped to RSSI_irq signal
Select IRQ_1 source in Tx mode
If Buffered_mode = 0
0 or 1 -> IRQ_1 is mapped to DCLK
0 or 1 -> IRQ_0 is set to low
if Buffered_mode = 1
0 -> IRQ_1 is mapped to Fifofull signal
1 -> IRQ_1 is mapped to TX_stopped signal
(IRQ_0 is mapped to /Fifoempty in Buffered mode)
FIFO full (IRQ source)
FIFO empty (IRQ source)
FIFO overrun error : Write
FIFO filling selection mode
0 -> The FIFO is filled if a pattern is detected
1 -> The FIFO is filled as long as Start_detect is high
Start of FIFO filling
If start_fill =
writing a
If start_fill =
clears the bit and wait for a new start sequence
30
, 1 -> start to fill the FIFO, 0 -> stop to fill the FIFO.
goes high when a start sequence is detected
clear FIFO after Overrun occurred
(6)
XE1205
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