am79c30a Advanced Micro Devices, am79c30a Datasheet - Page 97

• Manufacturer Part Number: am79c30a
• Description: Digital Subscriber Controller ?dsc ?circuit
• Manufacturer: Advanced Micro Devices

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The sidetone path defaults to –18-dB attenuation. If
disabling the sidetone path is desired, the sidetone
block must be enabled and programmed for infinite
attentuation.
Consider the LIU transformers, series resistors, and
IC LIU output drivers as a functional unit. Transform-
ers that meet CCITT I.430 requirements with other
transceivers are not necessarily appropriate for use
with the DSC circuit, and vice versa.
Interrupts should be masked when reading or writ-
ing any indirect or multibyte DSC circuit registers to
prevent the possibility of an interrupt occurring and
destroyed the contents of the Command Register.
If the MAP and secondary tone ringer are disabled,
the EAR, AREF, and LS outputs are high-imped-
ance. If the MAP is enabled, the unselected audio
output is high-impedance.
The MAP should not be enabled until after the LIU
has achieved synchronization. This will eliminate
the possibility of audible distortion when the internal
device timing is resynchronized to the S Interface.
Am79C30A/32A Data Sheet
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To make optimum use of the MAP digital signal pro-
cessing chain, use digital gain (GX) for fine adjust-
ment, and analog gain (GA) for coarse adjustment.
The user must program the Secondary Tone Ringer
Frequency Register (STFR) with a legal value be-
fore enabling the secondary tone ringer.
In order to exit Power-Down Mode due to LIU acti-
vation, both the F7 interrupt and the DSC/IDC cir-
cuit interrupt pin must be enabled. In order to exit
Power-Down Mode due to IOM-2 activation, both
the IOM-2 Timing Request interrupt and the
DSC/IDC circuit interrupt pin must be enabled.
The MAP auto-zero function must be enabled prior
to enabling the MAP. For all normal applications, the
auto-zero function should always be enabled.
To ensure proper operation of the filters (X and R)
and gains (GX, GR, GER, STGR, and ATGR), these
register blocks should not be accessed more fre-
quently than 128-µs intervals. This allows the inter-
nal buffers to the map to operate properly, since
they are updated only once per frame.
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