am79c30a Advanced Micro Devices, am79c30a Datasheet - Page 62

• Manufacturer Part Number: am79c30a
• Description: Digital Subscriber Controller ?dsc ?circuit
• Manufacturer: Advanced Micro Devices

Peripheral Port Interrupt Enable Register (PPIER) = 1
Default = Write = 00 Hex, Read = Bit 7 = 1, Bits 6–0 = 0
Address = Indirect C2 Hex, Read/Write
The Peripheral Port Interrupt Enable Register provides an individual interrupt-enable bit corresponding with eachof
the status conditions in the Peripheral Port Status Register. When set, the interrupt is enabled. Clearing the bit dis-
ables the interrupt. These bits are set and cleared by software.
Monitor Transmit Data Register (MTDR) Default = FF Hex
Address = Indirect C3 Hex, Write
The Monitor Transmit Data Register is the user-visible portion of the Monitor channel Transmitter Data buffer. Data
is written into this register by the user in response to a monitor transmit buffer available interrupt. It is then transmitted
to the receiver on the other side of the IOM-2 bus. The MTDR is emptied when the PP is reset.
Monitor Receive Data Register (MRDR) Default = 00 Hex
Address = Indirect C3 Hex, Read
The Monitor Receive Data Register is the user-visible portion of the Monitor channel Receiver Data buffer. Data is
written into this register by the hardware as it is received over the monitor channel. A monitor data available interrupt
is generated when the register is loaded. The register is overwritten by hardware only after the register has been
read. The default on reset is 00 hex.
62
Bit
7
Function
PP/MF Interrupt Enable—When set, this bit enables the Peripheral Port and Multiframing interrupts. When cleared, the
PP and MF interrupts are disabled.
Notes:
To ensure proper interrupt reporting, software must disable PP/MF interrupts when the interrupt routine is entered and
enable them when exiting.
INT EN
PP/MF
(MSB)
(MSB)
DATA
BIT 7
DATA
BIT 7
7
7
7
ENABL
IOM-2
RQST
TIME
DATA
BIT 6
DATA
BIT 6
6
6
6
ENABL
IN C/I1
CHNG
DATA
DATA
BIT 5
DATA
BIT 5
5
5
5
Am79C30A/32A Data Sheet
ENABL
IN C/I0
CHNG
DATA
DATA
BIT 4
DATA
BIT 4
4
4
4
MONTR
ABORT
RECVD
ENABL
DATA
BIT 3
DATA
BIT 3
3
3
3
MONTR
RECVD
ENABL
DATA
BIT 2
DATA
BIT 2
EOM
2
2
2
MONTR
ENABL
BUFFR
AVAIL
XMIT
DATA
BIT 1
DATA
BIT 1
1
1
1
MONTR
ENABL
RECV
AVAIL
(LSB)
(LSB)
DATA
DATA
BIT 0
DATA
BIT 0
0
0
0