am79c30a Advanced Micro Devices, am79c30a Datasheet - Page 55

• Manufacturer Part Number: am79c30a
• Description: Digital Subscriber Controller ?dsc ?circuit
• Manufacturer: Advanced Micro Devices

Monitor Channel Procedures
The Monitor channel operates on an event-driven ba-
sis; although data transfers on the bus are synchro-
nized to the frame sync, the flow of data is controlled by
a handshake procedure using the outgoing MX and in-
coming MR bits. Thus, the actual data rate is not fixed,
but is dependent upon the response speed of transmit-
ter and receiver. Figure 12 illustrates the sequence of
events in the monitor handshake procedure.
Idle State
The outgoing MX and incoming MR bits held inactive
for two or more frames indicates that the Monitor chan-
nel is Idle in the outgoing direction.
Start of Transmission
The PPCR1 register is programmed to select one of the
two monitor channels. Data is then loaded into the
monitor Transmit Data Register, causing the first data
byte to be presented to the bus as well as an inac-
tive-to-active transition of outgoing MX. The Monitor
channel transmit buffer available interrupt is also gen-
erated when data is placed on the bus, indicating that
the next data byte may be written to the buffer. Outgo-
ing MX remains active, and the data is repeated until an
inactive-to-active transition of the incoming MR is re-
ceived.
Subsequent Transmission
Following detection of the first inactive-to-active transi-
tion of incoming MR, all following bytes to be transmit-
ted will be presented to the bus coincident with an
active-to-inactive transition of outgoing MX. The IOM-2
specification defines a general case (Figure 12a) in
which the transmitter waits for an inactive-to-active
transition of incoming MR, and a maximum speed case
(Figure 12c) in which the transmitter achieves a higher
transmission rate by anticipating the falling edge of in-
coming MR.
The DSC/IDC circuit Monitor channel transmitter imple-
ments the maximum speed case as follows: the second
byte is placed onto the bus at the start of the frame fol-
lowing the transition of incoming MR (High to Low), and
a Monitor channel transmit buffer available interrupt is
generated. Simultaneously, outgoing MX is returned in-
active for one frame, then reactivated. Note that two
frames of outgoing MX inactive signifies the end of a
message. Outgoing MX and the data byte remain valid
until incoming MR goes inactive. The next byte is trans-
mitted during the next frame, meaning one frame after
incoming MR goes inactive. In this manner, the trans-
mitter is anticipating incoming MR returning active,
which it will do one frame time after it is deactivated, un-
less an abort is signaled from the receiver. After the last
Am79C30A/32A Data Sheet
byte of data has been transmitted, indicated by the
Monitor Transmit Data Register being empty and the
end-of-transmission (EOM) bit being set in PPCR1,
outgoing MX is deactivated in response to incoming
MR going inactive, and left inactive.
First Byte Reception
At the time the receiver sees the first byte, indicated by
the inactive-to-active transition of incoming MX, outgo-
ing MR is by definition inactive. Outgoing MR is acti-
vated in response to the activation of incoming MX, the
data byte on the bus is loaded into the Monitor Receive
Data Register, and a Monitor channel receive data
available interrupt is generated. Outgoing MR remains
active until the next byte is received or an end-of-mes-
sage is detected (incoming MX held inactive for two or
more frames).
Subsequent Reception
Data is received into the buffer on each falling edge of
incoming MX, and a Monitor channel receive data
available interrupt is generated. Note that the data was
actually valid at the time incoming MX became inactive,
one frame prior to becoming active. Outgoing MR is de-
activated at the time data is read and reactivated one
frame later. The reception of data is terminated by re-
ception of an end-of-message indication, which is in-
coming MX remaining inactive for two or more frames.
End-of-Transmission (EOM)
The transmitter sends an EOM in response to the EOM
request bit being set in PPCR1. Once the EOM bit is
set, the EOM is transmitted as soon as the Monitor
Transmit Data Register becomes empty. This is nor-
mally done when the last byte of a message has been
transmitted. The DSC/IDC circuit transmits an EOM
simply by not reactivating MX after deactivating it in re-
sponse to MR going inactive. The EOM request bit in
PPCR1 is automatically cleared when the EOM has
been transmitted, indicating that the monitor transmit-
ter is available for a new message.
Abort
An abort is a signal from the receiver to the transmitter
indicating that data has been missed. The receiver
sends an abort by holding MR inactive for two or more
frames in response to MX going active. An interrupt is
generated when an abort is received.
Flow Control
The transmitter is held off until the Monitor Receive
Data Register is read, since MR is held active until the
receive byte is read. The transmitter will not start the
next transmission cycle until MR goes inactive.
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