am79c30a Advanced Micro Devices, am79c30a Datasheet - Page 45

• Manufacturer Part Number: am79c30a
• Description: Digital Subscriber Controller ?dsc ?circuit
• Manufacturer: Advanced Micro Devices

D-Channel Status Register 1 — (DSR1) — Read Only
DSR1 has the format shown in Table 44.
The DSR1 bits generate interrupts and are set/reset under the conditions shown in Table 45 (in addition to a hard-
ware reset or Idle mode).
Bit Generate Interrupt
0
1
2
3
4
5
6
7
Bit
Yes, if DMR3 bit 0 = 1 Two bytes after an opening flag if a VA is
Yes, if DMR1 bit 3 = 1 When a closing flag is received
No
No
No
No
Yes, if DMR3 bit 1 = 1 When the closing flag is transmitted
No
0
1
2
3
4
5
6
7
Logical 1
Valid Address (VA) if the address decode logic is enabled or
End-of-Address (EOA) if the address decode logic is disabled
End of receive packet
Packet reception in progress
Loopback in operation at Am79C30A/32A
Loopback in operation at LIU
D-channel back-off not in operation
End of valid transmit packet
Current transmit packet has been aborted
Bit Set
decoded or address recognition is disabled
One byte after the opening flag of any packet,
valid or not
When the operation is in progress
When the operation is in progress
When the operation is in progress
When seven 1s and a 0 have been transmitted When the microprocessor reads DSR1 or when
Table 44. D-Channel Status Register 1
Am79C30A/32A Data Sheet
Table 45. DSR1 Interrupts
Bit Reset
When the microprocessor reads DSR1 or
associated DRCR
associated DRCR
When a flag or an abort is received
DTCR is loaded
DTCR is loaded
When the microprocessor reads DSR1 or
When the operation is not in progress
When the operation is not in progress
When the operation is not in progress
When the microprocessor reads DSR1 or when
Logical 0 (Default Value)
No valid address
Not end of packet
Packet not being received
No loopback in operation at Am79C30A/32A
No loopback in operation at LIU
D-channel back-off in operation
No end-of-transmit packet or no transmission
No transmit packet abort
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