am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 96

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

1-570
If a value other than those listed in the above table is de-
sired, CSR76 and CSR78 can be written after
initialization is complete. See the description of the ap-
propriate CSRs.
RDRA and TDRA
TDRA and RDRA indicate where the transmit and re-
ceive descriptor rings, respectively, begin. Each DRE
must be located on an 8-byte boundary.
LADRF
The Logical Address Filter (LADRF) is a 64-bit mask that
is used to accept incoming Logical Addresses. If the first
bit in the incoming address (as transmitted on the wire)
is a “1”, the address is deemed logical. If the first bit is a
“0”, it is a physical address and is compared against the
physical address that was loaded through the initializa-
tion block.
A logical address is passed through the CRC generator,
producing a 32-bit result. The high order 6 bits of the
CRC are used to select one of the 64 bit positions in the
Logical Address Filter. If the selected filter bit is set, the
address is accepted and the frame is placed into
memory.
The Logical Address Filter is used in multicast address-
ing schemes. The acceptance of the incoming frame
based on the filter value indicates that the message may
be intended for the node. It is the node’s responsibility to
AMD
R/TLEN
000
001
010
011
100
101
110
111
# of DREs
128
16
32
64
1
2
4
8
P R E L I M I N A R Y
Am79C961
determine if the message is actually intended for the
node by comparing the destination address of the stored
message with a list of acceptable logical addresses.
If the Logical Address Filter is loaded with all zeroes and
promiscuous mode is disabled, all incoming logical ad-
dresses except broadcast will be rejected.
The Broadcast address, which is all ones, does not go
through the Logical Address Filter and is handled as
follows:
1) If the Disable Broadcast Bit is cleared, the
2) If the Disable Broadcast Bit is set and promiscuous
3) If the Disable Broadcast Bit is set and promiscous
If external loopback is used, the FCS logic must be allo-
cated to the receiver (by setting the DXMTFCS bit in
CSR15, and clearing the ADD_FCS bit in TMD1) when
using multicast addressing.
PADR
This 48-bit value represents the unique node address
assigned by the IEEE and used for internal address
comparison. PADR[0] is the first address bit transmitted
on the wire, and must be zero. The six-hex-byte nomen-
clature used by the IEEE maps to the PCnet-ISA
controller PADR register as follows: the first byte com-
prises PADR[7:0], with PADR[0] being the least
significant bit of the byte. The second IEEE byte maps to
PADR[15:8], again from LSbit to MSbit, and so on. The
sixth byte maps to PADR[47:40], the LSbit being
PADR[40].
MODE
The mode register in the initialization block is copied into
CSR15 and interpreted according to the description of
CSR15.
broadcast address is accepted.
mode is enabled, the broadcast address is
accepted.
mode is disabled, the broadcast address is rejected.
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