am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 78

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

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5
AMD
LAPPEN
Look Ahead Packet Processing
(LAPPEN) . When set to a one,
the LAPPEN bit will cause the
PCnet-ISA
ate an interrupt following the
descriptor write operation to the
first buffer of a receive packet.
This interrupt will be generated in
addition to the interrupt that is
generated following the descrip-
tor write operation to the last
buffer of a receive packet. The in-
terrupt will be signaled through
the RINT bit of CSR0.
Setting LAPPEN to a one also
enables the PCnet-ISA
ler to read the STP bit of the
receive descriptors. PCnet-ISA+
controller will use STP informa-
tion to determine where it should
begin writing a receive packet’s
data. Note that while in this
mode, the PCnet-ISA
can write intermediate packet
data to buffers whose descriptors
do not contain STP bits set to
one. Following the write to the
last descriptor used by a packet,
the PCnet-ISA
scan through the next descriptor
entries to locate the next STP
bit that is set to a one. The
PCnet-ISA
writing the next packet’s data to
the buffer pointed to by that
descriptor.
Note that because several de-
scriptors may be allocated by the
host for each packet, and not all
messages may need all of the de-
scriptors
between descriptors that contain
STP = one, then some descrip-
tors/buffers may be skipped in
the ring. While performing the
search for the next STP bit that is
set to one, the PCnet-ISA
troller will advance through the
receive descriptor ring regard-
less of the state of ownership
bits. If any of the entries that are
examined during this search indi-
cate PCnet-ISA
OWN bit to zero in these entries.
If a scanned entry indicates host
ownership with STP=“0”, then
the PCnet-ISA
alter the entry, but will advance to
the next entry.
When the STP bit is found to be
true, but the descriptor that con-
tains this setting is not owned by
+
+
that
controller to gener-
controller will begin
+
+
+
controller will not
will RESET the
are
controller will
+
controller
P R E L I M I N A R Y
+
allocated
control-
+
con-
Am79C961
4
3
2-0
CSR4: Test and Features Control
Bit
15
DXMT2PD
ENTST
EMBA
Name
RES
the PCnet-ISA
the PCnet-ISA
stop advancing through the ring
entries and begin periodic polling
of this entry. When the STP bit is
found to be true, and the descrip-
tor that contains this setting is
owned by the PCnet-ISA
troller, then the PCnet-ISA
controller will stop advancing
through the ring entries, store the
descriptor information that is has
just read, and wait for the next re-
ceive to arrive.
This behavior allows the host
software to pre-assign buffer
space in such a manner that the
“header” portion of a receive
packet will always be written to a
particular memory area, and the
“data” portion of a receive packet
will always be written to a sepa-
rate memory area. The interrupt
is generated when the “header”
bytes have been written to the
“header” memory area.
Read/Write accessible always.
The LAPPEN bit will be reset
zero by RESET and will unaf-
fected
Appendix E for more information
on LAPP.
Disable
Deferral. (Described in the Media
Access Management section). If
DXMT2PD is set, Transmit Two
Part Deferral will be disabled.
DXMT2PD is cleared by RESET
and is not affected by STOP.
Enable
Algorithm. If EMBA is set, a modi-
fied
implemented as described in the
Media
section.
Read/Write accessible. EMBA is
cleared by RESET and is not af-
fected by STOP.
Reserved locations. Written as
zero and read as undefined.
Enable Test Mode operation.
When ENTST is set, writing to
test mode registers CSR124 and
CSR126 is allowed, and other
back-off
by
Access
Transmit
Description
Modified
the
+
+
controller, then
controller will
algorithm
STOP.
Management
Two
Back-off
+
con-
Part
See
is
+