am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 90

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

1-564
CSR108-109: Buffer Management Scratch
Bit
31-0 BMSCR
CSR112: Missed Frame Count
Bit
15-0
Internal Write
Lower 16-Bit
32-Bit word
AMD
(CSR104)
Operation
Name
Name
MFC
SRC[31:16]
SRC[15:0]
SRC[15:8]
SRC[7:0]
32-bit or 16-bit internal write op-
erations are performed. This
register is used internally by the
BIU/BMU as a word or byte
swapper. The swap register can
perform 32-bit operations that
the PC can not; the register is ex-
ternally
reasons only. CSR104 holds the
lower 16 bits and CSR105 holds
the upper 16 bits.
The swap function is defined as
follows:
Read/write accessible only when
STOP bit is set.
The Buffer Management Scratch
register is used for assembling
Receive and Transmit Status.
This register is also used as the
primary scan register for Buffer
Management
BMSCR register is undefined un-
til written.
Read/write accessible only when
STOP bit is set.
Counts the number of missed
frames.
This register is always readable
and is cleared by STOP.
A write to this register performs
an increment when the ENTST
bit in CSR4 is set.
When MFC is all 1’s (65535) and
a missed frame occurs, MFC in-
crements to 0 and sets MFC0 bit
(CSR4.9).
SWAP Register Result
accessible
Description
Description
Test
SWAP[15:0]
SWAP[31:16]
SWAP[ 7: 0]
SWAP[15:8]
P R E L I M I N A R Y
for
Modes.
test
Am79C961
CSR114: Receive Collision Count
Bit
15-0
CSR124: Buffer Management Unit Test
Bit
15-5
4
3
2-0
ISA Bus Configuration Registers
The ISA Bus Data Port (IDP) allows access to registers
which are associated with the ISA bus. These registers
are called ISA Bus Configuration Registers (ISACSRs),
and are indexed by the value in the Register Address
Port (RAP). The table below defines the ISACSRs which
GPSIEN
RCVCC
Name
Name
RES
RPA
RES
Counts the number of Receive
collisions seen, regular and late.
This register is always readable
and is cleared by STOP.
A write to this register performs
an increment when the ENTST
bit in CSR4 is set.
When RCVCC is all 1’s (65535)
and a receive collision occurs,
RCVCC increments to 0 and sets
RCVCC0 bit (CSR4.5)
This register is used to place the
BMU/BIU into various test modes
to support Test/Debug. This reg-
ister is writeable when the
ENTST bit in CSR4 is set.
Reserved locations. Written as
zero and read as undefined.
This
PCnet-ISA
GPSI Mode. This mode will
reconfigure the External Address
Pins so that the GPSI port is ex-
posed. This allows bypassing the
MENDEC- TMAU logic. This bit
should only be set if the external
logic supports GPSI operation.
Damage to the device may occur
in a non-GPSI configuration. Re-
fer to the GPSI section.
Runt Packet Accept. This bit
forces the CORE receive logic to
accept Runt Packets. This bit al-
lows for faster testing.
For test purposes only. Reserved
locations. Written as zero and
read as undefined.
mode
Description
Description
+
controller in the
places
the