am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 80

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

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0
CSR6: RCV/XMT Descriptor Table Length
Bit
15-12 TLEN
11-8
7-0
CSR8: Logical Address Filter, LADRF[15:0]
Bit
15-0 LADRF[15:0]
AMD
JABM
RLEN
Name
Name
RES
The JAB bit can be reset even if
the jabber condition is still
present.
JAB is set by the TMAU circuit
and cleared by writing a “1”. Writ-
ing a “0” has no effect. JAB is also
cleared by RESET or setting the
STOP bit.
Jabber Error Mask. If JABM is
set, the JAB bit in CSR4 will be
masked and will not set INTR flag
in CSR0.
JABM is set by RESET and is not
affected by STOP.
Contains a copy of the transmit
encoded ring length (TLEN) field
read from the initialization block
during PCnet-ISA
itialization. This field is written
during the PCnet-ISA
initialization routine.
Read accessible only when
STOP bit is set. Write operations
have no effect and should not be
performed. TLEN is only defined
after initialization.
Contains a copy of the receive
encoded ring length (RLEN) read
from the initialization block dur-
ing PCnet-ISA
zation. This field is written during
the PCnet-ISA
zation routine.
Read accessible only when
STOP bit is set. Write operations
have no effect and should not be
performed. RLEN is only defined
after initialization.
Reserved locations. Read as
zero. Write operations should not
be performed.
Logical Address Filter, LADRF
[15:0]. Undefined until initialized
either automatically by loading
the initialization block or directly
by an I/O write to this register.
Read/write accessible only when
STOP bit is set.
Description
Description
+
+
controller initiali-
controller initiali-
+
controller in-
+
controller
P R E L I M I N A R Y
Am79C961
CSR9: Logical Address Filter, LADRF[31:16]
Bit
15-0 LADRF[31:16] Logical
CSR10: Logical Address Filter, LADRF[47:32]
Bit
15-0 LADRF[47:32] Logical
CSR11: Logical Address Filter, LADRF[63:48]
Bit
15-0 LADRF[63:48] Logical
CSR12: Physical Address Register, PADR[15:0]
Bit
15-0 PADR[15:0]
Name
Name
Name
Name
LADRF[31:16]. Undefined until
initialized either automatically by
loading the initialization block or
directly by an I/O write to this
register.
Read/write accessible only when
STOP bit is set.
LADRF[47:32]. Undefined until
initialized either automatically by
loading the initialization block or
directly by an I/O write to this
register.
Read/write accessible only when
STOP bit is set.
LADRF[63:48]. Undefined until
initialized either automatically by
loading the initialization block or
directly by an I/O write to this
register.
Read/write accessible only when
STOP bit is set.
Physical
PADR[15:0]. Undefined until in-
itialized either automatically by
loading the initialization block or
directly by an I/O write to this
register. The PADR bits are
transmitted PADR[0] first and
PADR[47] last.
Read/write accessible only when
STOP bit is set.
Description
Description
Description
Description
Address
Address
Address
Address
Register,
Filter,
Filter,
Filter,