zl50021 Zarlink Semiconductor, zl50021 Datasheet - Page 85

• Manufacturer Part Number: zl50021
• Description: Enhanced 4 K Digital Switch With Stratum 3 Dpll
• Manufacturer: Zarlink Semiconductor

Note 1:
Note 2:
Note 3:
15 - 0
External Read/Write Addresses: 0058
Bit
Reset Value: 2E4A
UL[n]
15
15
The default value represents limit for 8 kHz input frequency, which is +6.4 µs (+10UI
When the MRLE bit of DPLLCR register is low, these registers are ignored. Depending on reference frequency (detected or
programmed through the Reference Frequency Register), the following values are used instead:
’h2E4A (10UIp-p of 1.544 MHz i.e. 6.4 µs) - if reference frequency is 8 kHz
’h002B (0.3UIp-p) - if reference frequency is 1.544 MHz
’h0025 (0.2UIp-p) - if reference frequency is 2.048 MHz
’h0011 (0.2UIp-p) - if reference frequency is 4.096 MHz
’h0007 (0.2UIp-p) - if reference frequency is 8.192 MHz
’h0002 (0.2UIp-p) - if reference frequency is 16.384 MHz
’h0002 (0.2UIp-p) - if reference frequency is 19.44 MHz
The name ‘upper’ is based on frequency.
UL[n]
14
14
UL[n]15 -
(n = 0 - 3)
Name
0
UL[n]
13
13
H
(see Note 1)
UL[n]
Reference n Single Period Upper Limit Bits: The binary value of these bits defines the
upper limit for the period of the REFn input, minus 1. The unit of the binary value is
measured in 100 MHz clock periods.
12
12
Table 52 - Upper Limit Register (RnULR) Bits, (n = 0 - 3)
UL[n]
11
11
H
, 005C
UL[n]
10
10
H
, 0060
UL[n]
H
Zarlink Semiconductor Inc.
9
9
, 0064
ZL50021
UL[n]
H
8
8
85
UL[n]
7
7
Description
UL[n]
6
6
UL[n]
5
5
UL[n]
4
p-p
4
of 1.544 MHz).
UL[n]
3
3
UL[n]
2
2
Data Sheet
UL[n]
1
1
UL[n]
0
0