zl50021 Zarlink Semiconductor, zl50021 Datasheet - Page 39

• Manufacturer Part Number: zl50021
• Description: Enhanced 4 K Digital Switch With Stratum 3 Dpll
• Manufacturer: Zarlink Semiconductor

11.2
When the device is in Divided Slave mode, STio0 - 31 are driven by CKi. In this mode, the output streams and
clocks have the same jitter characteristics as the input clock (CKi), but the input and output data rates cannot
exceed the limit defined by CKi (as per Table 1). For example, if CKi is 4.096 MHz, the input and output data rate
cannot be higher than 2.048 Mbps, and the generated output clock rates cannot exceed 4.096 MHz. If the DPLL is
not enabled, an external oscillator is optional in Divided Slave mode.
11.3
When the device is in Multiplied Slave mode, device hardware is used to multiply CKi internally. STio0 - 31 are
driven by this internally generated clock. In this mode, the output clocks and data can run at any of the specified
rates, but they may have different jitter characteristics from the input clock (CKi). The input data rates are still
limited by the CKi rate (as per Table 1), as input data are always sampled directly by CKi. If the DPLL is not
enabled, an external oscillator is not required in Multiplied Slave mode.
12.0
The DPLL accepts four input references and delivers six output clocks and five output frame pulses. The DPLL
meets or exceeds all of the requirements of the Telcordia GR-1244-CORE standard for a Stratum 3 compliant PLL.
This includes the freerun, reference switching and monitoring, jitter/wander attenuation and holdover functions. The
intrinsic output jitter of the DPLL does not exceed 1 ns (except for the 1.544 MHz output).
The input locking range of the DPLL is programmable, such that it can be larger than the strict Stratum 3
requirements.
The DPLL is able to lock to an input reference presented on the REF0 - 3 inputs. It is possible to force the DPLL
module to lock to a selected reference, to prefer one reference, to enter holdover mode or to freerun.
While in freerun mode, the DPLL is able to work in software mode which allows the user to program an output
frequency offset value through the microport of the device. Depending on the selected software mode, the DPLL
outputs can:
12.1
There are four timing modes for the DPLL: normal, holdover, automatic and freerun modes. In addition to these four
functional timing modes, the DPLL can also be programmed to internal reset mode.
12.1.1
In normal mode, the DPLL generates clocks and frame pulses that are phase locked to the active input reference.
Jitter on the input clock is attenuated by the DPLL.
a. gradually meet the given frequency offset (following pre-programmed phase alignment speed (phase
b. immediately, upon finishing the microport write, reach the given frequency offset, allowing an external
slope) and internal filter response), or
filter to be used.
Divided Slave Mode Operation
Multiplied Slave Mode Operation
DPLL Timing Modes
Overall Operation of the DPLL
Normal Mode
Zarlink Semiconductor Inc.
ZL50021
39
Data Sheet