zl50019gag2 Zarlink Semiconductor, zl50019gag2 Datasheet - Page 91
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zl50019gag2
Manufacturer Part Number
zl50019gag2
Description
Enhanced 2 K Digital Switch With Stratum 4e Dpll
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50019GAG2.pdf
(121 pages)
- Current page: 91 of 121
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25.1.2
When an external clock oscillator is used, numerous parameters must be considered. They include absolute
frequency, frequency change over temperature, output rise and fall times, output levels and duty cycle.
The output clock should be connected directly (not AC coupled) to the OSCi input of the device, and the OSCo
output should be left open as shown in Figure 24 on page 91. XC is a buffered version of the 20 MHz input clock
connected to the internal circuitry.
For applications requiring ±32 ppm clock accuracy, the following requirements should be met:
Frequency
Tolerance
Rise and Fall Time
Duty Cycle
External Clock Oscillator
XC
2 K DX
Figure 24 - Clock Oscillator Circuit
Zarlink Semiconductor Inc.
20.000 MHz
±32 ppm
10 ns
40% to 60%
ZL50019
OSCo
OSCi
No Connection
91
20 MHz OUT
+3.3 V
+3.3 V
GND
0.1 uF
Data Sheet
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