zl50019gag2 Zarlink Semiconductor, zl50019gag2 Datasheet - Page 67

• Manufacturer Part Number: zl50019gag2
• Description: Enhanced 2 K Digital Switch With Stratum 4e Dpll
• Manufacturer: Zarlink Semiconductor

Note 1:
Note: LDT should be calculated as per the maximum expected amplitude of jitter on the active input reference
using the following formula:
Example: If maximum expected jitter amplitude on 2.048 MHz reference is 10UI (i.e., 10 x 488.2 ns = 4882 ns)
(assuming the jitter frequency where DPLL attenuation is big), the LDT should be programmed to be (4882/15.2)
x 2 = 642 = 0282
Reset Value: 000F
External Read Only Address: 0045
External Read/Write Address: 0047
14 - 0
15 - 0
Bit
Bit
LDT
15
15
15
15
0
Output frequency offset, relative to master clock, will be represented as the following:
+10 ppm: CFN x 0.00001 = 440 = 01B8
-10 ppm: CFN x (-0.00001) = -440 = 7E48
FOF
LDT
14
14
14
14
FOF14 - 0
LDT15 - 0
Unused
Name
Name
H
FOF
LDT
13
13
13
13
H
Table 32 - Frequency Offset Register (FOR) Bits - Read Only
FOF
Reserved. In normal functional mode, this bit is zero.
Frequency Offset Bits: The binary value of these bits represents the current deviation
of the DPLL output from its center frequency. Defined in same units as CFN in the 2's
complement format.
LDT
Lock Detect Threshold Bits
The binary value of these bits defines the upper limit of the absolute phase from the
phase detector output for lock detection.
When the value of the absolute phase is less than or equal to LDT for duration of time
defined by the LDIR register, the DPLL locks.
When the value of the absolute phase is greater than LDT for duration of time defined by
the LDIR register divided by 256, the DPLL does not lock.
12
12
12
12
Table 33 - Lock Detector Threshold Register (LDTR) Bits
H
H
FOF
LDT
11
11
11
11
FOF
LDT
10
10
10
10
LDT = MAX_EXP_JITTER (ns) x 2
H
FOF
H
LDT
9
9
9
9
Zarlink Semiconductor Inc.
ZL50019
FOF
LDT
15.2 (ns)
8
8
8
8
67
FOF
LDT
7
7
7
7
Description
Description
FOF
LDT
6
6
6
6
FOF
LDT
5
5
5
5
FOF
LDT
4
4
4
4
FOF
LDT
3
3
3
3
FOF
LDT
2
2
2
2
Data Sheet
FOF
LDT
1
1
1
1
FOF
LDT
0
0
0
0