zl50019gag2 Zarlink Semiconductor, zl50019gag2 Datasheet - Page 106
zl50019gag2
Manufacturer Part Number
zl50019gag2
Description
Enhanced 2 K Digital Switch With Stratum 4e Dpll
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50019GAG2.pdf
(121 pages)
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† Characteristics are over recommended operating conditions unless otherwise stated.
* Test condition is R
the time taken to discharge C
AC Electrical Characteristics
1
2
3
4
STio Delay - Active to High-Z
STio Delay - High-Z to Active
Output Drive Enable (ODE) Delay
- High-Z to Active
Output Drive Enable (ODE) Delay
- Active to High-Z
ODE
STio
CKi @ 4.096 MHz
CKi @ 8.192 MHz
CKi @ 16.384 MHz
CKi @ 4.096 MHz
CKi @ 8.192 MHz
CKi @ 16.384 MHz
Characteristic
L
= 1 k, C
t
ZD_ODE
HiZ
L
L
.
= 30 pF; high impedance is measured by pulling to the appropriate rail with R
†
CKo0
- ST-BUS/GCI-Bus Output Tristate Timing
FPo0
STio
STio
Figure 39 - Serial Output and External Control
Figure 40 - Output Drive Enable (ODE)
Valid Data
t
t
ZD_ODE
DZ_ODE
Sym.
t
t
Zarlink Semiconductor Inc.
DZ
ZD
Valid Data
ZL50019
Tristate
t
DZ_ODE
106
Min.
-2
-3
-8
-2
-3
-8
t
t
DZ
ZD
V
Typ.
CT
Valid Data
Tristate
V
HiZ
CT
Max.
260
138
260
138
77
77
77
77
8
7
0
8
7
0
V
V
CT
CT
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
L
, with timing corrected to cancel
Master Mode
Multiplied Slave Mode
Divided Slave Mode
Master Mode
Multiplied Slave Mode
Divided Slave Mode
Master or
Multiplied Slave Mode
Divided Slave Mode
Master or
Multiplied Slave Mode
Divided Slave Mode
Test Conditions
Data Sheet
V
V
CT
CT
*
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