zl50019gag2 Zarlink Semiconductor, zl50019gag2 Datasheet - Page 113
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zl50019gag2
Manufacturer Part Number
zl50019gag2
Description
Enhanced 2 K Digital Switch With Stratum 4e Dpll
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50019GAG2.pdf
(121 pages)
- Current page: 113 of 121
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† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics
1
2
3
4
5
6
7
FPo5 Output Pulse Width
FPo5 Output Delay from the FPo5 falling edge
to the output frame boundary
FPo5 Output Delay from the output frame
boundary to the FPo5 rising edge
CKo5 Output Clock Period
CKo5 Output High Time
CKo5 Output Low Time
CKo5 Output Rise/Fall Time
Characteristic
†
- CKo5 (19.44 MHz) Timing (Only when DPLL is active)
Zarlink Semiconductor Inc.
ZL50019
113
t
rCK5
t
t
t
FODR5
Sym.
FODF5
t
t
t
FPW5
CKP5
CKH5
CKL5
, t
fCK5
Min.
49
22
21
50
23
24
Typ.
51
25
25
51
25
25
‡
Max.
55
28
32
53
27
28
5
Units
ns
ns
ns
ns
ns
ns
ns
Data Sheet
C
L
Notes
= 30 pF
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