zl50015qcg1 Zarlink Semiconductor, zl50015qcg1 Datasheet - Page 48

• Manufacturer Part Number: zl50015qcg1
• Description: Enhanced 1 K Channel Tdm Switch With Rate Conversion
• Manufacturer: Zarlink Semiconductor

Note: [n] denotes input stream from 0 - 15.
External Read/Write Address: 0100
Reset Value: 0000
15 - 9
5 - 4
3 - 0
8 - 6
15
0
Bit
14
0
13
0
STIN[n]SMP1 - 0
STIN[n]BD2 - 0
STIN[n]DR3 - 0
H
12
0
Unused
Name
Table 22 - Stream Input Control Register 0 - 15 (SICR0 - 15) Bits
11
0
10
0
H
- 010F
9
0
Reserved
In normal functional mode, these bits MUST be set to zero
Input Stream[n] Bit Delay Bits.
The binary value of these bits refers to the number of bits that the input stream
will be delayed relative to FPi. The maximum value is 7. Zero means no delay.
Input Data Sampling Point Selection Bits
Input Data Rate Selection Bits:
H
STIN[n]SMP1-0
STIN[n]
BD2
8
00
01
10
11
STIN[n]
Zarlink Semiconductor Inc.
BD1
7
ZL50016
STIN[n]DR3-0
STIN[n]
0101 - 1111
BD0
(2.048 Mbps, 4.096 Mbps, 8.192 Mbps
48
6
0000
0001
0010
0100
0011
STIN[n]
SMP1
5
Sampling Point
Description
streams)
3/4 point
1/4 point
2/4 point
4/4 point
STIN[n]
SMP0
4
Stream Unused
16.384 Mbps
2.048 Mbps
4.096 Mbps
8.192 Mbps
Data Rate
Reserved
STIN[n]
DR3
3
STIN[n]
DR2
2
.
STIN[n]
Sampling Point
DR1
(16.384 Mbps
1
streams)
2/4 point
4/4 point
Data Sheet
STIN[n]
DR0
0