zl50015qcg1 Zarlink Semiconductor, zl50015qcg1 Datasheet
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Page 1
... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved. Enhanced 1 K Digital Switch Ordering Information ZL50016GAC ZL50016QCC ZL50015QCG1 ZL50016GAG2 **Pb Free Tin/Silver/Copper • Per-stream input bit delay with flexible sampling point selection • ...
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... Users can employ the microprocessor port to perform register read/write, connection memory read/write, and data memory read operations. The port is configurable to interface with either Motorola or Intel-type microprocessors. The device also supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port. ZL50016 2 Zarlink Semiconductor Inc. Data Sheet 15 -1 pattern. On the ...
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... JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 17.1 Test Access Port (TAP 17.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 17.3 Test Data Registers 17.4 BSDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 18.0 Register Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 19.0 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 20.0 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 20.1 Memory Address Mappings 20.2 Connection Memory Low (CM_L) Bit Assignment 20.3 Connection Memory High (CM_H) Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 ZL50016 Table of Contents 3 Zarlink Semiconductor Inc. Data Sheet ...
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... DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 22.0 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 ZL50016 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 35 - Input and Output Frame Boundary Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 36 - FPo0 and CKo0 Timing Diagram Figure 37 - FPo1/3 and CKo1/3 Timing Diagram Figure 38 - FPo2 and CKo2 Timing Diagram Figure 39 - FPo3 and CKo3 Timing Diagram Figure 40 - Output Timing (ST-BUS Format ZL50016 List of Figures 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 29 - Address Map for Memory Locations (A13 = Table 30 - Connection Memory Low (CM_L) Bit Assignment when CMM = Table 31 - Connection Memory Low (CM_L) Bit Assignment when CMM = Table 32 - Connection Memory High (CM_H) Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 ZL50016 List of Tables 6 Zarlink Semiconductor Inc. Data Sheet ...
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... The following table captures the changes from October 2004 to January 2006. Page Item 13 Pin Description “CKi” on page 13 31 11.3, “Output Clock Frequencies“ ZL50016 Updated Ordering Information. • Clarified pin description for CKi. • Added new section to describe output clock frequencies. 7 Zarlink Semiconductor Inc. Data Sheet Change Change ...
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... CORE CORE CORE D11 D13 STOHZ1 D3 D8 D14 D12 D15 Zarlink Semiconductor Inc. Data Sheet CKi IC_Open IC_Open IC_GND ODE V STio15 SS FPo_ IC_GND STio13 V STio14 DD_IO OFF1 V DD_ V V ...
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... Zarlink Semiconductor Inc. Data Sheet 148 146 144 142 140 138 136 134 132 130 NC 128 NC NC 126 NC 124 NC VSS 122 NC VDD_IO 120 NC ...
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... ZL50016 Power Supply for the core logic: +1.8 V Power Supply for analog circuitry: +1.8 V Power Supply for I/O: +3.3 V DD_IO Power Supply for the CKo5 and CKo3 outputs: +3 Ground SS 10 Zarlink Semiconductor Inc. Data Sheet Description ...
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... JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG is not enabled. Internal Test Mode (5 V-Tolerant Input with Internal Pull-down) These pins may be left unconnected. Internal Test Mode Enable (5 V-Tolerant Input) These pins MUST be low. 11 Zarlink Semiconductor Inc. Data Sheet ...
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... These two pins should be tied together and are typically used to select CKi = 4.096 MHz operation. See Table 7, “ZL50016 Operating Modes” on page 31 for a detailed explanation. See Table 13, “Control Register (CR) Bits” on page 38 for CKi and FPi selection using the CKIN1 - 0 bits. 12 Zarlink Semiconductor Inc. Data Sheet ...
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... MHz clock must be used. By default, the clock falling edge defines the input frame boundary, but the device allows the clock rising edge to define the frame boundary by programming the CKINP bit in the Control Register (CR). 13 Zarlink Semiconductor Inc. Data Sheet Input (5 V-Tolerant ...
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... STOHZ0 - 7. When it is high, STio0 - 15 and STOHZ0 - 7 are enabled. When it is low, STio0 - 15 are tristated and STOHZ0 - 7 are driven high. Data Bus V-Tolerant Slew-Rate-Limited Three-state I/Os) These pins form the 16-bit data bus of the microprocessor port. 14 Zarlink Semiconductor Inc. Data Sheet ...
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... Upon releasing the reset signal to the device, the first microprocessor access cannot take place for at least 600 µs due to the time required to stabilize the device from the power-down state. Refer to Section Section 13.2 on page 32 for details. 15 Zarlink Semiconductor Inc. Data Sheet ...
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... Mbps, eight of the streams are operating at 8.192 Mbps or all streams operating at 4.096 Mbps. With all streams operating at 2.048 Mbps, the capacity will be reduced to 512 channels. However, as each stream can be programmed to a different data rate, any combination of data rates can be achieved, as long as the total channel ZL50016 16 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 1 - CKi and FPi Configurations for Divided Clock Modes ZL50016 7 CKIN 1-0 Bits Input Clock Rate (CKi) 00 16.384 MHz 01 8.192 MHz 10 4.096 MHz 17 Zarlink Semiconductor Inc. Data Sheet Input Frame Pulse (FPi) 8 kHz (61 ns wide pulse) 8 kHz (122 ns wide pulse) 8 kHz (244 ns wide pulse) ...
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... Figure 4 - Input Timing when CKIN1 - 0 bits = “10” in the CR ZL50016 CKIN 1-0 Bits Input Clock Rate (CKi) 00 16.384 MHz 01 8.192 MHz 10 4.096 MHz Channel Zarlink Semiconductor Inc. Data Sheet Input Frame Pulse (FPi) 8 kHz (61 ns wide pulse) 8 kHz (122 ns wide pulse) 8 kHz (244 ns wide pulse) Channel ...
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... Mbps) Figure 6 - Input Timing when CKIN1 - 0 = “00” in the CR ZL50016 Channel Channel N = 127 5 4 Channel N = 255 Zarlink Semiconductor Inc. Data Sheet ...
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... The following figures describe the usage of the FPO0P, FPO1P, FPO2P, FPO3P, CKO0P, CKO1P, CKO2P and CKO3P bits to generate the FPo0 - 3 and CKo0 - 3 timing. ZL50016 Output Timing Rate 244 4.096 122 8.192 61 16.384 244, 122 4.096, 8.192, 16.384 or 32.768 Table 3 - Output Timing Generation 20 Zarlink Semiconductor Inc. Data Sheet Output Timing Unit ns MHz ns MHz ns MHz ns MHz ...
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... Figure 7 - Output Timing for CKo0 and FPo0 CKOFPO1EN = 1 FPO1P = 0 FPO1POS = 0 CKOFPO1EN = 1 FPO1P = 1 FPO1POS = 0 CKOFPO1EN = 1 FPO1P = 0 FPO1POS = 1 CKOFPO1EN = 1 FPO1P = 1 FPO1POS = 1 CKOFPO1EN = 1 CKO1P = 0 CKo1 = 8.192 MHz CKOFPO1EN = 1 CKO1P = 1 CKo1 = 8.192 MHz Figure 8 - Output Timing for CKo1 and FPo1 ZL50016 21 Zarlink Semiconductor Inc. Data Sheet ...
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... When CKOFPO3SEL1-0 = “01,” the output for FPo3 and CKo3 follow the same as Figure 8: Output Timing for CKo1 and FPo1 When CKOFPO3SEL1-0 = “10,” the output for FPo3 and CKo3 follow the same as Figure 9: Output Timing for CKo2 and FPo2 Figure 10 - Output Timing for CKo3 and FPo3 with CKoFPo3SEL1-0=”11” ZL50016 22 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 11 - Input Bit Delay Timing Diagram (ST-BUS) ZL50016 Channel 0 Channel Bit Delay = 1 Channel 0 Channel Zarlink Semiconductor Inc. Data Sheet Channel 2 Channel 2 ...
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... Figure 12 - Input Bit Sampling Point Programming ZL50016 Last Channel Sampling Point = 1/4 Bit Last Channel Last Channel Zarlink Semiconductor Inc. Data Sheet Sampling Point = 3/4 Bit Channel Channel Sampling Point = 1/2 Bit Channel Sampling Point = 4/4 Bit Channel ...
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... ST-BUS formatting). The output advancement is enabled by STO[n] (bits the Stream Output Control Register (SOCR0 - 15) as described in Table 24 on page 51. The output bit advancement can vary from bits. ZL50016 Nominal Channel n+1 Boundary Zarlink Semiconductor Inc. Data Sheet 111 11 111 00 111 10 111 01 ...
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... Channel Fractional Bit Advancement = 1/4 Bit Last Channel Channel Fractional Bit Advancement = 1/2 Bit Last Channel Channel Fractional Bit Advancement = 3/4 Bit Channel Zarlink Semiconductor Inc. Data Sheet Channel 2 Channel 1 Channel 2 Channel ...
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... In variable delay mode, the delay depends on the combination of the source and destination channels of the input and output streams. ZL50016 HiZ CH2 CH3 STOHZ Advancement (Programmable in 4 steps of 1/4 bit for 2.048 Mbps, 4.096 Mbps and 8.192 Mbps Programmable in 2 steps of 1/2 bit for 16.384 Mbps) 27 Zarlink Semiconductor Inc. Data Sheet Last-2 Last-1 Last CH0 ...
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... CH4 CH5 CH6 CH7 CH8 CH9 CH4 CH5 CH6 CH7 CH8 CH9 CH4 CH5 CH6 CH7 CH8 CH9 CH4 CH5 CH6 CH7 CH8 CH9 frames + ( Zarlink Semiconductor Inc. Data Sheet n n-m > 7 STio < STi STio >= STi n-m Frame L-2 L-1 CH0 CH1 CH2 CH3 ...
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... Frame L-2 L-1 CH0 CH1 CH2 CH3 L-2 L-1 CH0 CH1 CH2 CH3 L-2 L-1 CH0 CH1 CH2 CH3 L-2 L-1 CH0 CH1 CH2 CH3 29 Zarlink Semiconductor Inc. Data Sheet Frame L-2 L-1 CH0 CH1 CH2 CH3 L-2 L-1 CH0 CH1 CH2 CH3 L-2 L-1 CH0 CH1 CH2 CH3 L-2 L-1 CH0 CH1 CH2 CH3 ...
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... CKi rate in either Multiplied or Divided Clock modes, because input data are always sampled directly by CKi. ZL50016 Zarlink Semiconductor Inc. Data Sheet BPD2 BPD1 BPD0 0 0 ...
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... Reference Lock CKi OPM CKo0 8/ CKi MULT 8/16 M Table 7 - ZL50016 Operating Modes Table 8 - Generated Output Frequencies 31 Zarlink Semiconductor Inc. Data Sheet Output Clock Pins Data Pins Enabled Clock Source CKo0-3 STi CKi Yes CKi CKo0-3 (CKi) CKo0-3 (CKi MULT) STo ...
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... Note: If CKi is 16.384 MHz, the waiting time is 500 µs; if CKi is 8.192 MHz, the waiting time is 1 ms; if CKi is 4.096 MHz, the waiting time is 2 ms. ZL50016 supply (normally +3 established before the DD_IO supply may be powered up at the same time DD_CORE supply by more than 0.3 V. DD_IO 32 Zarlink Semiconductor Inc. Data Sheet ...
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... ST[n]SBER (bit 0) in the BRCR to high. There must be at least 2 frames (250 µs) between completion of connection memory programming and starting the BER receiver before the BER receiver can correctly identify BER errors bit BER counter is used to count the number of bit errors. ZL50016 15 -1 pseudorandom code (ITU O.151). 33 Zarlink Semiconductor Inc. Data Sheet ...
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... Quadrant 1 Channel Channel Channel Channel Channel Channel Channel 64 - 127 Channel 128 - 191 34 Zarlink Semiconductor Inc. Data Sheet Data Coding (V/D bit = 1) No code Alternate Bit Inversion (ABI) Inverted Alternate Bit Inversion (ABI) All bits inverted Quadrant 2 ...
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... ZL50016 Action Normal Operation Replaces LSB of every channel in Quadrant y with ‘0’ Replaces LSB of every channel in Quadrant y with ‘1’ Replaces MSB of every channel in Quadrant y with ‘0’ Replaces MSB of every channel in Quadrant y with ‘1’ 35 Zarlink Semiconductor Inc. Data Sheet ...
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... The Device Identification Register - The JTAG device ID for the ZL50016 is 0C36014B Version Part Number Manufacturer ID LSB 17.4 BSDL A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the IEEE-1149.1 test interface. ZL50016 <31:28> 0000 <27:12> 1100 0011 0110 <11:1> 0001 0100 101 < ...
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... IMS SRR OCFCR OCFSR FPOFF0 FPOFF1 FPOFF2 IFR BERFR0 BERLR0 SICR0 - 15 SIQFR0 - 15 SOCR0 - 15 BRSR0 - 15 BRLR0 - 15 BRCR0 - 15 BRER0 - 15 37 Zarlink Semiconductor Inc. Data Sheet Reset By Switch/Hardware Switch/Hardware Hardware Only Hardware Hardware Hardware Hardware Hardware Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware ...
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... FPIN CKINP FPINP CKIN POS 1 Description CKIN1 - 0 FPi Active Period 122 ns 10 244 ns 11 Table 13 - Control Register (CR) Bits 38 Zarlink Semiconductor Inc. Data Sheet CKIN VAR MBPE OSB MS1 MS0 0 EN CKi 16.384 MHz 8.192 MHz 4.096 MHz ...
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... HiZ Active (Controlled by CM) Memory Selection 00 Connection Memory Low Read/Write 01 Connection Memory High Read/Write 10 Data Memory Read 11 Reserved 39 Zarlink Semiconductor Inc. Data Sheet VAR MBPE OSB MS1 MS0 0 EN STOHZ0 - 7 Driven High Driven High Driven High ...
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... STIO_ 0 BDL RBER PD_EN EN Description BDL STio0 - 15 Operation 0 normal operation: STi0-15 are inputs STio0-15 are outputs 1 bi-directional operation: STi0-15 tied low internally STio0-15 are bi-directional 40 Zarlink Semiconductor Inc. Data Sheet TBER BPD BPD BPD MBPS ...
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... Table 15 - Software Reset Register (SRR) Bits ZL50016 STIO_ 0 BDL RBER PD_EN EN Description Description 41 Zarlink Semiconductor Inc. Data Sheet TBER BPD BPD BPD MBPS SRST 0 SW ...
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... When this bit is low, CKo0 and FPo0 are in high impedance state. Table 16 - Output Clock and Frame Pulse Control Register (OCFCR) Bits ZL50016 FPOF2 FPOF1 FPOF0 Description 42 Zarlink Semiconductor Inc. Data Sheet CKO CKO CKO CKO FPO3 FPO2 FPO1 FPO0 EN EN ...
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... CKO2 FPO2 FPO2 P POS P P POS Description CKOFPO3 FPo3 SEL1 - 0 00 244 ns 01 122 Zarlink Semiconductor Inc. Data Sheet CKO1 FPO1 FPO1 CKO0 FPO0 P P POS P P CKo3 4.096 MHz 8.192 MHz 16.384 MHz 32.768 MHz ...
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... Note: In Divided Clock modes, CKo3 - 1 cannot exceed frequency of CKi. Table 17 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits (continued) ZL50016 FPO3 FPO3 CKO2 FPO2 FPO2 P POS P P POS Description 44 Zarlink Semiconductor Inc. Data Sheet CKO1 FPO1 FPO1 CKO0 FPO0 P P POS FPO0 POS ...
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... Data Rate FPo_OFF[n] (Mbps) Pulse Cycle Width 2.048 one 4.096 MHz clock 4.096 one 8.192 MHz clock 8.192 one 16.384 MHz clock 16.384 one 16.384 MHz clock 45 Zarlink Semiconductor Inc. Data Sheet FOF[n] FOF[n] FOF[n] FOF[n] FOF[n] OFF2 OFF1 OFF0 ...
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... Description BER BER BER BER BER BER F10 Description 46 Zarlink Semiconductor Inc. Data Sheet OUT IN ERR ERR BER BER BER BER BER ...
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... Note: [n] denotes input stream from 0 - 15. Table 21 - BER Receiver Lock Register 0 (BERLR0) Bits - Read Only ZL50016 BER BER BER BER BER BER L10 Description 47 Zarlink Semiconductor Inc. Data Sheet BER BER BER BER BER ...
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... Sampling Point (2.048 Mbps, 4.096 Mbps, 8.192 Mbps streams) 00 3/4 point 01 1/4 point 10 2/4 point 11 4/4 point STIN[n]DR3-0 0000 0001 0010 0011 0100 0101 - 1111 48 Zarlink Semiconductor Inc. Data Sheet STIN[n] STIN[n] STIN[n] STIN[n] DR3 DR2 DR1 DR0 . Sampling Point (16.384 Mbps streams) ...
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... LSB of each channel is replaced by “0” 101 LSB of each channel is replaced by “1” 110 MSB of each channel is replaced by “0” 111 MSB of each channel is replaced by “1” 49 Zarlink Semiconductor Inc. Data Sheet STIN[n] STIN[n] STIN[n] STIN[n] ...
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... STIN[n]Q0C2-0 0xx 100 LSB of each channel is replaced by “0” 101 LSB of each channel is replaced by “1” 110 MSB of each channel is replaced by “0” 111 MSB of each channel is replaced by “1” 50 Zarlink Semiconductor Inc. Data Sheet STIN[n] STIN[n] STIN[n] STIN[n] ...
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... Mbps, 4.096 Mbps, 8.192 Mbps streams 1/4 bit 10 2/4 bit 11 3/4 bit STIN[n]DR3 - 0 0000 0001 0010 0011 0100 0101 - 1111 51 Zarlink Semiconductor Inc. Data Sheet STO[n] STO[n] STO[n] STO[n] STO[n] AD0 DR3 DR2 DR1 DR0 Additional Advancement (16.384 Mbps streams) ...
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... Table 26 - BER Receiver Length Register [n] (BRLR[n]) Bits ZL50016 ST[n] ST[n] ST[n] BRS7 BRS6 BRS5 Description ST[n] ST[n] ST[n] ST[n] BL8 BL7 BL6 BL5 Description 52 Zarlink Semiconductor Inc. Data Sheet ST[n] ST[n] ST[n] ST[n] ST[n] BRS4 BRS3 BRS2 BRS1 BRS0 ST[n] ST[n] ST[n] ST[n] ST[n] BL4 BL3 BL2 BL1 BL0 ...
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... Table 28 - BER Receiver Error Register [n] (BRER[n]) Bits - Read Only ZL50016 Description ST[n] ST[n] ST[n] ST[n] ST[n] ST[n] BC10 BC9 BC8 BC7 BC6 Description 53 Zarlink Semiconductor Inc. Data Sheet ST[n] ST[n] CBER SBER ST[n] ST[n] ST[n] ST[n] ST[n] BC5 BC4 BC3 BC2 BC1 BC0 0 ...
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... Stream Stream Zarlink Semiconductor Inc. Data Sheet Channel Address (Ch0 - 255 Channel [ (Note ...
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... CM_H bits should be set before Bit 15 (UAEN bit) is set to high. Table 30 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0 ZL50016 SSA SSA SCA SCA SCA Description 55 Zarlink Semiconductor Inc. Data Sheet SCA SCA SCA SCA SCA CMM ...
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... MSG MSG MSG MSG MSG Description PC PC Channel Output Mode Per Channel Tristate 0 1 Message Mode 1 0 BER Test Mode Zarlink Semiconductor Inc. Data Sheet MSG MSG PCC PCC CMM Reserved ...
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... A-law w/o ABI µ-law w/o Magnitude 11 Inversion Output Coding Law OCL1-0 For Voice (V/D bit = 0) 00 CCITT.ITU A-law CCITT.ITU µ-law 01 10 A-law w/o ABI µ-law w/o Magnitude 11 Inversion 57 Zarlink Semiconductor Inc. Data Sheet V/D ICL ICL OCL OCL For Data (V/D bit = 1) ...
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... Sym. Min. Typ. Max. I 115 DD_CORE I DD_IO Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0.5 5.0 V -0.5 2 -0.5 7 1.5 W ° +125 . ‡ Typ. Max. Units °C 25 +85 3.3 3.6 V 1.8 1.89 V 3.3 ...
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... Characteristics are over recommended operating conditions unless otherwise stated. ALL SIGNALS Figure 19 - Timing Parameter Measurement Voltage Levels ZL50016 Sym. Level V 0 DD_IO V 0 DD_IO V 0 DD_IO Timing Reference Points 59 Zarlink Semiconductor Inc. Data Sheet Units Conditions ...
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... AKH t 8 AKZ , with timing corrected to cancel time taken CSS t RWS t AS VALID ADDRESS VALID READ DATA AKD 60 Zarlink Semiconductor Inc. Data Sheet 2 Units Test Conditions pF (Note 1) ...
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... AKH t 8 AKZ , with timing corrected to cancel time taken CSS t RWS t AS VALID ADDRESS t DS VALID WRITE DATA t AKD 61 Zarlink Semiconductor Inc. Data Sheet 2 Units Test Conditions pF (Note 1) ...
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... AKH t 8 AKZ , with timing corrected to cancel time taken CSD VALID ADDRESS VALID READ DATA AKD 62 Zarlink Semiconductor Inc. Data Sheet 2 Units Test Conditions pF (Note 1) ...
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... AKH t 8 AKZ , with timing corrected to cancel time taken CSD VALID ADDRESS t DS VALID WRITE DATA t AKD 63 Zarlink Semiconductor Inc. Data Sheet 2 Units Test Conditions pF (Note 1) ...
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... TMSS t 10 TMSH t 20 TDIS t 60 TDIH t TDOD t 200 TRSTW t t TCKL TCKH t TCKP t TMSH t TDIH t TDOD Figure 24 - JTAG Test Port Timing Diagram 64 Zarlink Semiconductor Inc. Data Sheet ‡ Typ. Max. Units Notes TRSTW ...
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... FPIW t 45 FPIS t 45 FPIH t 110 CKIP t 55 CKIH t 55 CKIL t CKi, t CKi CVC 65 Zarlink Semiconductor Inc. Data Sheet ‡ Typ. Max. Units Notes 61 115 ‡ Typ. Max. Units Notes 122 220 ...
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... CKIH t CKIL t CKi, t CKi CVC t FPIW t FPIS FPIH t CKIH t rCKI t FPIW t FPIS FPIH t CKIH t rCKI 66 Zarlink Semiconductor Inc. Data Sheet ‡ Min. Typ. Max. Units Notes 90 244 420 ns 110 ns 110 ns 220 244 270 ns 110 135 ns 110 135 ...
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... Ch0 t SIS4 t SIH4 Bit7 Bit6 Ch0 Ch0 t SIS8 t SIH8 Bit7 Bit6 Bit5 Bit4 Bit3 Ch0 Ch0 Ch0 Ch0 Ch0 67 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions Bit6 V CT Ch0 Bit5 Bit4 V CT Ch0 Ch0 V Bit2 Bit1 ...
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... SIH2 Bit0 Ch0 t SIS4 t SIH4 Bit0 Bit1 Ch0 Ch0 t SIS8 t SIH8 Bit1 Bit2 Bit3 Bit4 Ch0 Ch0 Ch0 Ch0 68 Zarlink Semiconductor Inc. Data Sheet V Bit2 Bit1 Bit0 Ch0 Ch0 Ch0 Bit1 V CT Ch0 Bit2 Bit3 V CT Ch0 Ch0 V Bit5 Bit6 ...
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... Bit0 Ch255 Ch255 Ch0 16.384 Mbps Input Frame Boundary Figure 30 - GCI-Bus Input Timing Diagram when Operated at 16 Mbps ZL50016 SIS16 t SIH16 Bit1 Bit2 Bit3 Bit4 Ch0 Ch0 Ch0 Ch0 69 Zarlink Semiconductor Inc. Data Sheet V Bit5 Bit6 Bit7 Ch0 Ch0 Ch0 ...
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... Ch0 t SOD16 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Ch0 Ch0 Ch0 Ch0 Ch0 Ch0 Ch0 Ch0 70 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions Multiplied Clock Mode Divided Clock Mode Bit6 Ch0 Bit5 Bit4 ...
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... Ch0 Ch0 Ch0 Ch0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Ch0 Ch0 Ch0 Ch0 Ch0 Ch0 Ch0 Ch1 71 Zarlink Semiconductor Inc. Data Sheet Bit1 V CT Ch0 Bit2 Bit3 V CT Ch0 Ch0 Bit5 Bit6 Bit7 V Ch0 Ch0 Ch0 CT Bit1 Bit2 ...
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... Valid Data Tristate t ZD Tristate Valid Data t DZ_ODE Valid Data HiZ Figure 34 - Output Drive Enable (ODE) 72 Zarlink Semiconductor Inc. Data Sheet Max. Units Test Conditions 7 ns Multiplied Clock Mode 0 ns Divided Clock Mode 7 ns Multiplied Clock Mode 0 ns Divided Clock Mode ...
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... Input Frame Boundary FPo0 CKo0 (4.096 MHz) Figure 35 - Input and Output Frame Boundary Offset ZL50016 ‡ Sym. Min. Typ. Max. t FBOS FBOS t FBOS Output Frame Boundary 73 Zarlink Semiconductor Inc. Data Sheet Units Notes ns ns Input reference jitter is equal to zero. ...
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... CKP03 t CKH03 t CKL03 rCK03 fCK03 Sym. Min. t FPW03 t FODF03 t FODR03 t CKP03 t CKH03 t CKL03 rCK03 fCK03 74 Zarlink Semiconductor Inc. Data Sheet FODR03 t CKL03 rCK03 ‡ Typ. Max. Units Notes 239 244 249 117 127 ns L 117 ...
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... Sym. Min. t 106 FPW13 t 56 FODF13 t 46 FODR13 t 106 CKP13 t 46 CKH13 t 46 CKL13 rCK13 fCK13 75 Zarlink Semiconductor Inc. Data Sheet rCK13 ‡ Typ. Max. Units Notes 122 127 122 127 ...
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... FODR23 t CKP23 t CKH23 t CKL23 rCK23 fCK23 Sym. Min. t FPW23 t FODF23 t FODR23 t CKP2 t CKH23 t CKL23 rCK23 fCK23 76 Zarlink Semiconductor Inc. Data Sheet FODR23 t CKL23 rCK23 ‡ Typ. Max. Units Notes ...
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... FODF3 t FODR3 t CKP3 t CKH3 t CKL3 rCK3 fCK3 Sym. Min. t FPW3 t FODF3 t FODR3 t CKP3 t CKH3 t CKL3 rCK3 fCK3 77 Zarlink Semiconductor Inc. Data Sheet FODR3 t CKL3 rCK3 ‡ Typ. Max. Units Notes 27 30 30.5 ...
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... FPo0 CKo0 (4.096 MHz) CKo1 (8.192 MHz) CKo2 (16.384 MHz) CKo3 (32.768 MHz) ZL50016 t FPD t C1D t C2D t C3D Figure 40 - Output Timing (ST-BUS Format) 78 Zarlink Semiconductor Inc. Data Sheet Sym. Min. Max. Units C1D C2D C3D Sym ...
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... Zarlink Semiconductor 2003 All rights reserved. 1 ISSUE 214440 ACN 26June03 DATE APPRD. Package Code Previous package codes ...
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... Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...