zl50015qcg1 Zarlink Semiconductor, zl50015qcg1 Datasheet - Page 16

• Manufacturer Part Number: zl50015qcg1
• Description: Enhanced 1 K Channel Tdm Switch With Rate Conversion
• Manufacturer: Zarlink Semiconductor

3.0
The device has sixteen ST-BUS/GCI-Bus inputs (STi0 - 15) and sixteen ST-BUS/GCI-Bus outputs (STio0 - 15).
STio0 - 15 can also be configured as bi-directional pins, in which case STi0 - 15 will be ignored. It is a non-blocking
digital switch with 1024 64 kbps channels and is capable of performing rate conversion between ST-BUS/GCI-Bus
inputs and ST-BUS/GCI-Bus outputs. The ST-BUS/GCI-Bus inputs accept serial input data streams with data rates
of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps on a per-stream basis. The ST-BUS/GCI-Bus outputs
deliver serial data streams with data rates of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps on a
per-stream basis. The device also provides eight high impedance control outputs (STOHZ0 - 7) to support the use
of external ST-BUS/GCI-Bus tristate drivers for the first eight sixteen ST-BUS/GCI-Bus outputs (STio0 -7).
By using Zarlink’s message mode capability, microprocessor data stored in the connection memory can be
broadcast to the output streams on a per-channel basis. This feature is useful for transferring control and status
information for external circuits or other ST-BUS/GCI-Bus devices.
The device uses the ST-BUS/GCI-Bus input frame pulse (FPi) and the ST-BUS/GCI-Bus input clock (CKi) to define
the input frame boundary and timing for sampling the ST-BUS/GCI-Bus input streams with various data rates. The
output data streams will be driven by and have their timing defined by FPi and CKi in Divided Clock mode (CLKM
bit 11 Table 13, Control Register (CR) Bits. In Multiplied Clock mode, the output data streams will be driven by an
internally generated clock, which is multiplied from CKi internally. In Multiplied Clock mode, the output data streams
will be driven by an internally generated clock, which is multiplied from CKi internally. Refer to Application Note
ZLAN-120 for further explanation of the different modes of operation.
There are two clock modes for this device:
The first is the Divided Clock mode. In this mode, output streams are clocked by input CKi. Therefore the output
streams have exactly the same jitter as the input streams. The output data rate can be the same as or lower than
the input data rate, but the output data rate cannot be higher than what CKi can drive. For example, if CKi is
4.096 MHz, the output data rate cannot be higher than 2.048 Mbps.The second clock mode is called Multiplied
Clock mode. In this mode, CKi is used to generate a 16.384 MHz clock internally, and output streams are driven by
this internal clock. In Multiplied Clock mode, the data rate of output streams can be any rate, but output jitter may
not be exactly the same as input jitter.
A Motorola or Intel compatible non-multiplexed microprocessor port allows users to program the device to operate
in various modes under different switching configurations. Users can use the microprocessor port to perform
internal register and memory read and write operations. The microprocessor port has a 16-bit data bus, a 14-bit
address bus and six control signals (MOT_INTEL, CS, DS_RD, R/W_WR and DTA_RDY).
The device supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.
4.0
The ZL50016 has 16 serial data inputs and 16 serial data outputs. Each stream can be individually programmed to
operate at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. Depending on the data rate there will be 32
channels, 64 channels, 128 channels or 256 channels, respectively, during a 125 µs frame.
The output streams can be programmed to operate as bi-directional streams. By setting BDL (bit 6) in the Internal
Mode Selection (IMS) register, the input streams 0 - 15 (STi0 - 15) are internally tied low, and the output streams 0
- 15 (STio0 - 15) are set to operate in a bi-directional mode.The input data rate is set on a per-stream basis by
programming STIN[n]DR3 - 0 (bits 3 - 0) in the Stream Input Control Register 0 - 15 (SICR0 - 15). The output data
rate is set on a per-stream basis by programming STO[n]DR3 - 0 (bits 3 - 0) in the Stream Output Control Register
0 - 15 (SOCR0 - 15). The output data rates do not have to match or follow the input data rates. The maximum
number of channels switched is limited to 1024 channels. If all 16 input streams were operating at 16.384 Mbps
(256 channels per stream), this would result in 4096 channels. Memory limitations prevent the device from
operating at this capacity. A maximum capacity of 1024 channels will occur if four of the streams are operating at
16.384 Mbps, eight of the streams are operating at 8.192 Mbps or all streams operating at 4.096 Mbps. With all
streams operating at 2.048 Mbps, the capacity will be reduced to 512 channels. However, as each stream can be
programmed to a different data rate, any combination of data rates can be achieved, as long as the total channel
Device Overview
Data Rates and Timing
Zarlink Semiconductor Inc.
ZL50016
16
Data Sheet