mt9092apr1 Zarlink Semiconductor, mt9092apr1 Datasheet - Page 5

• Manufacturer Part Number: mt9092apr1
• Description: Fully Featured Digital Telephone Circuit With Embedded Hdlc Transceiver And Dsp For Tone Generations And Hands Free Operation
• Manufacturer: Zarlink Semiconductor

MT9092
Data Sheet
sign/Inverted Magnitude coding, respectively. Optionally, sign- magnitude coding may also be selected for
proprietary applications.
The Filter/CODEC block also implements transmit and receive audio path gains in the analog domain. These gains
are in addition to the digital gain pad provided in the DSP section and provide an overall path gain resolution of
0.5dB. A programmable gain, voice side-tone path is also included to provide proportional transmit speech
feedback to the handset receiver so that a dead sounding handset is not encountered. Figure 3 depicts the nominal
half-channel and side-tone gains for the HPhone-II.
On PWRST (pin 6) the Filter/CODEC defaults such that the side-tone path, dial tone filter and 400 Hz transmit filter
are off, all programmable gains are set to 0 dB and µ-Law companding is selected. Further, the Filter/CODEC is
powered down due to the PuFC bit (Transducer Control Register, address 0Eh) being reset. This bit must be set
high to enable the Filter/CODEC.
The internal architecture is fully differential to provide the best possible noise rejection as well as to allow a wide
dynamic range from a single 5 volt supply design. This fully differential architecture is continued into the Transducer
Interface section to provide full chip realization of these capabilites.
A reference voltage (V
), for the conversion requirements of the CODER section, and a bias voltage (V
), for
Ref
Bias
biasing the internal analog sections, are both generated on-chip. V
is also brought to an external pin so that it
Bias
may be used for biasing any external gain plan setting amplifiers. A 0.1 µF capacitor must be connected from V
Bias
may only be used internally, a 0.1 µF capacitor from the V
to analog ground at all times. Likewise, although V
Ref
Ref
pin to ground is required at all times. It is suggested that the analog ground reference point for these two capacitors
be physically the same point.
To facilitate this the V
and V
pins are situated on adjacent pins.
Ref
Bias
The transmit filter is designed to meet CCITT G.714 specifications. The nominal gain for this filter path is 0 dB (gain
control = 0 dB).
An anti-aliasing filter is included. This is a second order lowpass implementation with a corner
frequency at 25 kHz. Attenuation is better than 32 dB at 256 kHz and less than 0.01 dB within the passband.
An optional 400 Hz high-pass function may be included into the transmit path by enabling the Tfhp bit in the
Transducer Control Register (address 0Eh). This option allows the reduction of transmitted background noise such
as motor and fan noise.
The receive filter is designed to meet CCITT G.714 specifications. The nominal gain for this filter path is 0 dB (gain
control = 0 dB). Filter response is peaked to compensate for the sinx/x attenuation caused by the 8 kHz sampling
rate.
The Rx filter function can be altered by enabling the DIAL EN control bit in the Transducer Control Register
(address 0Eh). This causes another lowpass function to be added, with a 3 dB point at 1000 Hz. This function is
intended to improve the sound quality of digitally generated dial tone received as PCM.
Transmit sidetone is derived from the Tx filter and is subject to the gain control of the Tx filter section. Sidetone is
summed into the receive path after the Rx filter gain control section so that Rx gain adjustment will not affect
sidetone levels. The side-tone path may be enabled/disabled with the SIDE EN bit located in the Transducer
Control Register (address 0Eh). See also STG
-STG
(address 0Bh).
0
2
Transmit and receive filter gains are controlled by the TxFG
-TxFG
and RxFG
-RxFG
control bits respectively.
0
2
0
2
These are located in the FCODEC Gain Control Register 1 (address 0Ah). Transmit filter gain is adjustable from
0 dB to +7 dB and receive filter gain from 0 dB to -7 dB, both in 1 dB increments.
Side-tone filter gain is controlled by the STG
-STG
control bits located in the FCODEC Gain Control Register 2
0
2
(address 0Bh). Side-tone gain is adjustable from -9.96 dB to +9.96 dB in 3.32 dB increments.
Law selection for the Filter/CODEC is provided by the A/µ companding control bit while the coding scheme is
controlled by the sign-mag/CCITT bit. Both of these reside in the General Control Register (address 0Fh).
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