mt9092apr1 Zarlink Semiconductor, mt9092apr1 Datasheet - Page 21

• Manufacturer Part Number: mt9092apr1
• Description: Fully Featured Digital Telephone Circuit With Embedded Hdlc Transceiver And Dsp For Tone Generations And Hands Free Operation
• Manufacturer: Zarlink Semiconductor

Watchdog
To maintain program integrity an on-chip watchdog timer is provided for connection to the microcontroller reset pin.
The watchdog output WD (pin 17) goes high while the HPhone-II is held in reset via the PWRST (pin 6). Release of
PWRST will cause WD to return low immediately and will also start the watchdog timer. The watchdog timer is
clocked on the falling edge of F0i and requires only this input, along with V
If the watchdog reset word is written to the watchdog register (address 11h) after PWRST is released, but before
the timeout period (T=512 mSec) expires, a reset of the timer results and WD will remain low. Thereafter, if the
reset word is loaded correctly at intervals less than 'T' then WD will continue low. The first break from this routine, in
which the watchdog register is not written to within the correct interval or it is written to with incorrect data, will result
in a high going WD output after the current interval 'T' expires. WD will then toggle at this rate until the watchdog
register is again written to correctly.
5-BIT WATCHDOG RESET WORD
x=don’t care
Test Loops
Detail LBio and LBoi Loopback Register (address 16h)
LBio
LBoi
Setting this bit causes data on DSTi to be looped back to DSTo directly at the pins. The appropriate
Setting this bit causes data on DSTo to be looped back to DSTi directly at the pins.
channel enables Ch
0
EN -Ch
X
3
EN must also be set.
X
Zarlink Semiconductor Inc.
X
MT9092
W4
0
21
W3
1
W2
0
W1
1
DD
, for operation.
W0
0
Data Sheet