mt9092apr1 Zarlink Semiconductor, mt9092apr1 Datasheet - Page 30

• Manufacturer Part Number: mt9092apr1
• Description: Fully Featured Digital Telephone Circuit With Embedded Hdlc Transceiver And Dsp For Tone Generations And Hands Free Operation
• Manufacturer: Zarlink Semiconductor

Note: Bits marked "-" are reserved bits and should be written with logic "0".
C-Channel Register
Timing Control Register
Loop-back Register
All bits active high:
Ch
Ch
Ch
LB
LB
Micro-port access to the ST-BUS C-Channel information.
2
1
0
io
oi
EN and Ch
EN
EN
Active high enables data from the ST-BUS input to be looped back to the ST-BUS output directly at the pins. The DSTo tri-state driver
Active high enables data from ST-BUS output to be looped back to the ST-BUS input directly at the pins.
must also be enabled using one of the channel enable signals.
3
EN
D
-
Channels 2 and 3 are the B1 and B2 channels, respectively. PCM associated with the DSP, Filter/CODEC and transducer audio
Transmit B1 and B2 data on DSTo
Receive B1 and B2 data on DSTi
Channel 1 conveys the control/status information for the layer 1 transceiver. The full 64kb/s bandwidth is available and is assigned
Channel 0 conveys the D-Channel HDLC information. Since this function is dedicated to 16kb/s operation, only the first two bits of
paths is conveyed in one of these channels as selected in the timing control register.
according to which transceiver is being used. Consult the data sheets for the transceiver selected. When high register data is trans-
mitted on DSTo. When low this timeslot is tri-stated on DSTo. Receive C-Channel data (DSTi) is always routed to the register
regardless of this control bit's logic state.
the octet are required; the remaining six bits of the D-Channel octet carry no information and are tri-stated. When high HDLC data
is transmitted on DSTo. When low DSTo is forced to logic 0 for the two least significant bit positions. Incoming DSTi data is
-
7
7
7
7
When high PCM from the Filter/CODEC and DSP is transmitted on DSTo in the associated channel. When low DSTo is
When enabled PCM from DSTi is routed to the DSP and Filter/CODEC in the associated channel. If both Ch
forced to logic 0 for the corresponding timeslot. If both Ch
are enabled, data input defaults to channel 2.
LBio
D
-
6
6
6
6
LBoi
D
5
5
5
-
5
D
-
-
4
4
4
4
CH
Zarlink Semiconductor Inc.
D
-
3
3
3
3
EN
3
MT9092
CH
30
D
-
2
2
2
2
2
EN
CH
2
EN and Ch
D
1
1
-
1
1
1
EN
CH
ADDRESS = 16h WRITE/READ VERIFY
ADDRESS = 15h WRITE/READ VERIFY
3
D
EN are enabled, data defaults to channel 2.
0
0
-
0
0
0
EN
ADDRESS 17h-1Ch are RESERVED
ADDRESS = 14h WRITE/READ
Power Reset Value
Power Reset Value
Read = Not Applicable
Power Reset Value
Write = 1111 1111
X00X XXXX
XX0X 0000
2
EN and Ch
Data Sheet
3
EN