mt9092apr1 Zarlink Semiconductor, mt9092apr1 Datasheet - Page 25

• Manufacturer Part Number: mt9092apr1
• Description: Fully Featured Digital Telephone Circuit With Embedded Hdlc Transceiver And Dsp For Tone Generations And Hands Free Operation
• Manufacturer: Zarlink Semiconductor

Note: Bits marked "-" are reserved bits and should be written with logic "0".
HDLC Status Register
Intgen
Idle Chan
RxBS2,
RxBS1
Note
Txstat2,
Txstat1
Rxstat2,
Rxstat1
Is set to a 1 when an interrupt (in conjunction with the Interrupt Mask Register) has been generated by the HDLC. This is an
Is set to a 1 when an Idle Channel state (15 or more ones) has been detected by the receiver. This is an asynchronous event. Status
Indicates the status of the next byte to be read from the Rx FIFO.
- If two consecutive first byte signals are received without an intervening last byte, then an overflow has occurred and the first packet
- On power-up these bits are in an indeterminate state until the first byte is written to Rx FIFO.
These two bits are encoded to indicate the present state of Tx FIFO. This is an asynchronous event.
These two bits are encoded to indicate the present state of Rx FIFO. This is an asynchronous event.
asynchronous event. It is reset when the Interrupt Register is read.
becomes valid after first 15 bits or the first zero bit received.
(or packets) are bad. A bad packet indicates that either a frame abort has occurred or the FCS did not match.
Intgen
RxBS2
Txstat2
Rxstat2
7
1
0
1
0
0
0
1
1
0
0
1
1
Chan
Idle
6
RxBS1
Txstat1
Rxstat1
1
1
0
0
0
1
1
0
0
1
1
0
RxBS2 RxBS1 Txstat
5
Byte status
Tx FIFO Status
Rx FIFO Status
last byte (bad packet)
first byte
last byte (good packet)
packet byte
TxFULL
5 OR MORE BYTES (15 if Fltx set)
4 OR LESS BYTES (14 if Fltx set)
TxEMPTY
RxEMPTY
14 OR LESS BYTES (4 if Flrx set)
15 OR MORE BYTES (5 if Flrx set)
RxOVERFLOW EXISTS
4
Zarlink Semiconductor Inc.
2
3
MT9092
Txstat
25
2
1
Rxstat
1
2
Rxstat
0
1
ADDRESS = 04h READ
Power Reset Value
00XX 1000
Data Sheet