mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 19

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mt90528ag2

Manufacturer Part Number
mt90528ag2
Description
28-port Primary Rate Circuit Emulation Aal1 Sar
Manufacturer
Zarlink Semiconductor
Datasheet
2.11.5
Overall UDT Cell Counter
Within each VC’s SDT Reassembly Control Structure, there is a bit (V = VC Arrival) which is set each time
that a cell arrives on the VC. CPU monitoring of this bit can be used to provide per-VC timeout monitoring.
In addition to the counters themselves, if one of the following per-VC counters rolls over and the
corresponding service enable bit for the counter is set, a status field indicates the address in internal
memory of the last SDT Reassembly Control Structure to generate a serviceable event.
Overall SDT Cell Counter
Per-VC Write Overrun Counter
Per-VC Late Cell Arrival Counter
Per-VC Reassembled Cell Counter
Per-VC AAL1-byte Header Error Counter
Per-VC AAL1-byte Sequence Error Counter
Per-VC Lost Cell Counter
Per-VC Misinserted Cell Counter
Per-VC Pointer Reframe Counter
Per-VC Pointer Parity Error Counter
Per-VC Write Underrun Counter
Per-VC Write Overrun Counter
SDT RX_SAR Module
Zarlink Semiconductor Inc.
MT90528
19
Data Sheet

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