mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 139

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

Address: 2042 (Hex)
Label: SRSER
Reset Value: 0000 (Hex)
SDT_MIS_ROLL_
REFRAME_ROLL
SDT_HDR_ROLL
SDT_SEQ_ROLL
POINTER_OUT_
CAS_CHANGE_
PARITY_ROLL_
OF_RANGE_SE
SDT_UNDER_
SDT_REASS_
SDT_OVER_
SDT_LOST_
ROLL_SE
ROLL_SE
ROLL_SE
ROLL_SE
Reserved
Label
_SE
_SE
_SE
SE
SE
SE
Position
15:11
Bit
10
0
1
2
3
4
5
6
7
8
9
Table 53 - SDT Reassembly Service Enable Register
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/O
When set, the assertion of the Reassembled Cells Counter Rollover status bit in an SDT
Reassembly Control Structure will cause the SDT_RXSAR_STATUS bit to be set in the
SDT Reassembly Status Register at 2044h.
When set, the assertion of the AAL1 Header Byte Error Counter Rollover status bit in an
SDT Reassembly Control Structure will cause the SDT_RXSAR_STATUS bit to be set in
the SDT Reassembly Status Register at 2044h.
When set, the assertion of the AAL1 Sequence Error Counter Rollover status bit in an SDT
Reassembly Control Structure will cause the SDT_RXSAR_STATUS bit to be set in the
SDT Reassembly Status Register at 2044h.
When set, the assertion of the Lost Cells Counter Rollover status bit in an SDT Reassem-
bly Control Structure will cause the SDT_RXSAR_STATUS bit to be set in the SDT Reas-
sembly Status Register at 2044h.
When set, the assertion of the Misinserted Cells Counter Rollover status bit in an SDT
Reassembly Control Structure will cause the SDT_RXSAR_STATUS bit to be set in the
SDT Reassembly Status Register at 2044h.
When set, the assertion of the Pointer Reframes Counter Rollover status bit in an SDT
Reassembly Control Structure will cause the SDT_RXSAR_STATUS bit to be set in the
SDT Reassembly Status Register at 2044h.
When set, the assertion of the Pointer Parity Counter Rollover status bit in an SDT Reas-
sembly Control Structure will cause the SDT_RXSAR_STATUS bit to be set in the SDT
Reassembly Status Register at 2044h.
When set, the assertion of the Buffer Underrun Counter Rollover status bit in an SDT
Reassembly Control Structure will cause the SDT_RXSAR_STATUS bit to be set in the
SDT Reassembly Status Register at 2044h.
When set, the assertion of the Buffer Overrun Counter Rollover status bit in an SDT Reas-
sembly Control Structure will cause the SDT_RXSAR_STATUS bit to be set in the SDT
Reassembly Status Register at 2044h.
When set, the assertion of the Pointer Out-of-Range status bit in an SDT Reassembly
Control Structure will cause the SDT_RXSAR_STATUS bit to be set in the SDT Reassem-
bly Status Register at 2044h.
When set, the assertion of the CAS Changed status bit in an SDT Reassembly Control
Structure will cause the SDT_RXSAR_STATUS bit to be set in the SDT Reassembly Status
Register at 2044h.
Always reads “0000_0”.
Zarlink Semiconductor Inc.
MT90528
139
Description
Data Sheet