mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 107

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

The range of the phase detector is therefore based upon the wander tolerance at 0.1 Hz and will be 32 UI peak-to-
peak (+/- 16 UI).
The maximum intrinsic output jitter allowed on the output of the PLL is specified in ITU-T G.823/G.824 and is listed
in Table 24. That said, the PLL within the MT90528 has a maximum intrinsic output jitter of one half of an MCLK
cycle. However, any jitter on MCLK will be directly transferred to the output clocks.
MTIE (Maximum Time Interval Error)
ANSI T1.403 and T1.101 require that the output phase change at a speed of no more than 81 ns per 1.326 ms, with
a maximum phase change of 1 Ps. Therefore, the slew rate of the DCO input is no more than 61 ppm of the center
frequency setting. The “no more than 81 ns / 1.326 ms” requirement is met in all modes.
Since the period of the 1.544 MHz, 2.048 MHz, and 4.096 MHz signals is less than 1 Ps, that requirement is met
automatically when the PLL is in synchronous mode. When switching between modes, the 1 Ps MTIE is not
guaranteed.
Locking Range
When using an 8 kHz, 2.048 MHz, or 4.096 MHz input clock, a locking range of + 246 ppm is provided. When the
input clock is 1.544 MHz, the locking range is +245 ppm. Note that the locking range is related to the master clock.
If the master clock (i.e., MCLK) is 100 ppm too low, the whole locking range also shifts 100 ppm downwards.
4.8
The MT90528 contains an IEEE 1149 standard Test Access Port (TAP), which provides Boundary-Scan test access
to aid board-level testing. (IEEE 1149 is often referred to by its older designation: JTAG - Joint Test Action Group.)
4.8.1
The test port is a standard IEEE 1149 interface, with the optional TRST pin. The Test Access Port consists of 5 pins:
Test Interface
Test Access Port
TCK: Boundary-scan Test Clock.
TDI: Test Data In; input pin clocked in on the rising edge of TCK. TDI should be pulled HIGH if bound-
ary-scan is not in use.
TDO: Test Data Out; output pin updated on the falling edge of TCK. The output is in high-impedance
except when data is actually being shifted out.
TMS: Test Mode Select; input control line clocked in on the rising edge of TCK. TMS should be pulled
HIGH if boundary-scan is not in use.
TRST: Test Reset; asynchronous, active-low, input which is used to reset the JTAG interface, and the
TAP controller. The TRST pin has an internal pull-down, and should also be pulled LOW externally
Clock
C1M5
C2M
Table 23 - Minimum Input Wander and Jitter Tolerance
Table 24 - Maximum Allowed Intrinsic Output Jitter
A0 [UI
28
37
pp
Clock
C1M5
C2M
]
Zarlink Semiconductor Inc.
A1 [UI
MT90528
18
5
A [UI
pp
107
]
0.1
0.2
pp
F0 [Hz]
]
1.2E-5
1.2E-5
A [ns]
65
98
F1 [Hz]
10
20
@ 0.1 Hz
6.2
23
Data Sheet