mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 186
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mt90528ag2
Manufacturer Part Number
mt90528ag2
Description
28-port Primary Rate Circuit Emulation Aal1 Sar
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90528AG2.pdf
(195 pages)
- Current page: 186 of 195
- Download datasheet (3Mb)
Figure 69 illustrates the connections from the external pins of the UTOPIA interface to an ATM device, when the
MT90528 device is operating in PHY mode.
ATM Device
Note 1: The ATM device is not required to drive the UTOPIA clock. The UTO_IN_CLK and UTO_OUT_CLK pins of
the MT90528 can either be inputs or outputs.
Note 2: When in PHY mode, UTO_IN_ENBATM_CLAVPHY, UTO_IN_SOC, UTO_OUT_ENBATM_CLAVPHY and
UTO_OUT_SOC should be pulled down. It is also recommended to pull up UTO_IN_CLAVATM_ENBPHY and
UTO_OUT_CLAVATM_ENBPHY.
RxData[15:0]
TxData[15:0]
RxAddr[4:0]
TxAddr[4:0]
Figure 69 - PHY Mode: External UTOPIA Pin Connections
RxEnb*
RxSOC
TxEnb*
TxSOC
RxClav
TxClav
RxPrty
TxPrty
RxClk
TxClk
UTO_IN_PAR
UTO_OUT_ADD[4:0]
UTO_OUT_CLK
UTO_OUT_CLAVATM_ENBPHY
UTO_OUT_ENBATM_CLAVPHY
UTO_OUT_DATA[15:0]
UTO_OUT_SOC
UTO_OUT_PAR
UTO_IN_CLK
UTO_IN_CLAVATM_ENBPHY
UTO_IN_ENBATM_CLAVPHY
UTO_IN_DATA[15:0]
UTO_IN_SOC
UTO_IN_ADD[4:0]
Zarlink Semiconductor Inc.
MT90528
186
RX UTOPIA
TX UTOPIA
RX Parity
TX Parity
Interface
Interface
MT90528
Mode)
(PHY
Data Sheet
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