mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 205

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

Table 182 - Sync (Sync, CRC-4 Remote, Alarms, MAS and Phase) Interrupt Mask Register (Address Y44)
Bit
15-9
15
14
13
12
Bit
8
7
6
5
4
3
2
1
0
RCRCRM
RSLPM
Name
TXUNDERIM
RXOVFLIM
YM
(0)
(0)
(0)
#
EOPDIM
EOPRIM
TEOPIM
RXFFIM
TXFLIM
Name
GAIM
FAIM
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
#
not used.
Remote CRC-4 and RAI Mask. This is the mask bit for the RCRCRI interrupt status bit in the
Sync (Sync, CRC-4 Remote, Alarms, MAS and Phase) Interrupt Status Register (address
Y34). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit
is zero, the corresponding interrupt bit will function normally.
Receive Slip Mask. This is the mask bit for the RSLPI interrupt status bit in the Sync (Sync,
CRC-4 Remote, Alarms, MAS and Phase) Interrupt Status Register (address Y34). If this
mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit is zero, the
corresponding interrupt bit will function normally.
Receive Y-bit Mask. This is the mask bit for the YI interrupt status bit in the Sync (Sync,
CRC-4 Remote, Alarms, MAS and Phase) Interrupt Status Register (address Y34). If this
mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit is zero, the
corresponding interrupt bit will function normally.
Table 181 - HDLC Interrupt Mask Register (Address Y43) (E1)
not used.
GAIM When unmasked an interrupt is generated when go-ahead pattern (01111111)
was detected by the HDLC receiver.
End of Packet Data Interrupt Mask.When unmasked an interrupt is initiated when an
end of packet (EOP) byte was written into the RX FIFO by the HDLC receiver.
Transmit End of Packet Interrupt Mask.When unmasked an interrupt is initiated
when the byte about to be read from the RX FIFO is the last byte of the packet. An
interrupt is also initiated if the Rx FIFO is read and there is no data in it.
End of Packet Received Interrupt Mask.When unmasked an interrupt is initiated
when the byte about to be read from the RX FIFO is the last byte of the packet. An
interrupt is also initiated if the Rx FIFO is read and there is no data in it.
Transmit Fifo Low Interrupt Mask.When unmasked an interrupt is initiated when the
Tx FIFO is emptied below the selected low threshold level.
Transmit Elastic Buffer full interrupt Mask. When unmasked an interrupt is initiated
whenever the transmit elastic buffer is full.If 1 - masked, 0 - unmasked.
Transmit Fifo Underrun Interrupt Mask. interrupt is initiated for TX FIFO underrun
indication.
Receive Fifo full Threshold interrupt Mask. When unmasked an interrupt is initiated
whenever the Rx FIFO is filled above the selected full threshold level.
Receive Fifo Overflow Interrupt Mask. When unmasked an interrupt is initiated
whenever the 16 byte RX FIFO overflowed (i.e. an attempt to write to a 16 byte full RX
FIFO).
Zarlink Semiconductor Inc.
MT9072
Functional Description
(E1)
205
Functional Description
Data Sheet