mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 105

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

Test Data Input (TDI) - Serial input data applied to this port is fed either into the instruction register or into a test
data register, depending on the sequence previously applied to the TMS input. Both registers are described in a
subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is internally
pulled up to device V
Test Data Output (TDO) - Depending on the sequence previously applied to the TMS input, the contents of either
the instruction register or data register are serially shifted out towards the TDO pin. The data out of TDO is clocked
on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDO driver is
set to a high impedance state.
Test Reset (TRST) - Reset the JTAG scan structure.
16.2
The TAP Controller generates clock and control signals for the Instruction Register (IR) and the Test Data Registers
(TDR’s). The TAP Controller operates synchronously with the TCK input clock and responds to the TMS input
signal to generate control signals which shift, capture, or update data through either the IR or the TDR’s.
16.3
The Instruction Register (IR) is a 3-bit register which allows one of four test instructions to be shifted into the device.
Test instructions are serially loaded into the IR from the TDI pin by the TAP Controller. Refer to Table 53 which
describes the test instructions provided by the MT9072; these instructions are in accordance with the IEEE 1149.1
standard.
Note 1. The following optional JTAG instructions are not supported, INTEST, RUNBIST and USERCODE.
MSB
0
0
0
1
Test Access Port (TAP) Controller
Instruction Register
0
1
0
1
LSB
0
0
1
1
SAMPLE/PR
Instruction
EXTEST
IDCODE
BYPASS
DD
ELOAD
Name
when it is not driven from an external source.
This instruction isolates the framer logic (on chip logic) from the input and output
pins. The signal states at the output pins are determined by the values
programmed (earlier) in the Boundary Scan Register. This instruction allows
testing of board level interconnects (i.e., open, stuck at, bridge).
This instruction performs two functions. On the rising edge of TCK, the SAMPLE
instruction is performed. With this instruction, the signal states at the input and
output pins are loaded into the Boundary Scan Register. On the falling edge of
TCK, the PRELOAD instruction is performed. With this instruction, the signal
states at the output pins is determined by the values programmed (earlier) in the
Boundary Scan Register.
This instruction forces the value of the 32 bit MT9072 Identification Register into
the Instruction Register’s parallel output latches. This is the default instruction
loaded after a JTAG reset.
This instruction connects the Bypass Register between the TDI and TDO pins.
Table 53 - JTAG Instruction Register
Zarlink Semiconductor Inc.
MT9072
105
Functional Description
Data Sheet