mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 176

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

15-2
1-0
15-7
Bit
Bit
6
5
4
3
2
1
0
SIP1-0 Signaling Interrupt Period. These 2 bits determine the signaling Interrupt period due to the
CNCLR
ACCLR
Name
RxTRS
TxTRS
Name
ELAS
CSIG
RST
#
(0)
(0)
(0)
(0)
(0)
(0)
(0)
#
Table 145 - DL, CCS, CAS and Other Control Register (R/W Address Y03) (E1)
not used.
Receive signaling changes. This 2 bits determine the duration of the signaling interrupt bit
CASRI(Y36).
00
01
10
not used.
Elastic Buffer Enable. When this bit is set to one, the data at DSTo is a 2.048 Mb/s serial output
stream which contains all 32 timeslots of the received PCM30 link data after HDB3 decoding.
This data does not pass through the elastic buffer and is clocked out with the falling edge of
EXCLi. The data at the DSTo pin is identical to the data at the RXDL pin. When this bit is set to
zero, the elastic buffer is enabled, and DSTo operates synchronously with the clock at the CKi
pin.
Note that only RXDLC or the EXCL can be used to clock DSTo data and DSTo data has no
relationship to CKi when ELAS is1.
Automatic Counter Clear. When this bit is set to one, all non-latched status counters (address
Y15 to Y1A) are cleared automatically by the one second timer bit ONESEC (address Y11)
immediately following the counter latch operation (address Y25 to Y2B). If zero, all non-latched
status counters operate normally.
Receive Transparent Mode. If one, the framing function is disabled on the receive side. Data
coming from the receive line passes through the slip buffer and drives DSTo with an arbitrary
alignment. When zero, the receive framing function operates normally.
Transmit Transparent Mode. If one, the MT9072 is in transmit transparent mode where no
framing or signaling is imposed on data transmitted from DSTi onto the PCM30 line. In other
words, timeslot 0 and timeslot 16 data on the transmit PCM30 link is sourced from the DSTi
input. If zero, the MT9072 is in termination mode.
CCS and CAS signaling. If one, the MT9072 is in Common Channel signaling (CCS) mode. If
zero, the MT9072 is in Channel Associated signaling (CAS) mode.
Counter Clear. When this bit is changed from zero to one, all non-latched status counters
(address Y15 to Y1A) are cleared. If zero, all non-latched status counters operate normally.
Reset. When this bit is changed from zero to one, the selected framer (Y) will reset to its default
mode. See the Reset Operation section for the default settings.
Table 146 - Signaling Period Interrupt Word (R/W Address Y04) (E1)
2 msec Period
8 msec Period
16 msec Period
Zarlink Semiconductor Inc.
MT9072
Functional Description
Functional Description
176
Data Sheet