mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 116

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

15
12
6-5
Bit
14
13
10
11
9
8
7
4
3
TRANSP
T1DM
RS1-0
REFR
Name
G.802
JYEL
CXC
ESF
IMA
(00)
FSI
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
#
Inverse Mux for ATM Mode. Setting this bit high allows the IO port to be easily connected to one
of the Zarlink IMA devices such as MT90220. DSTi becomes a serial 1.544 Mb/s data stream.
C4b becomes a 1.544 MHz clock that clocks DSTi in on the falling edge. RXFPB becomes a
positive framing pulse that is high for the first bit of the serial T1 stream coming from the DSTo
pin. The data from DSTo is clocked out on the rising edge of RXDLC. Set this pin low for all other
applications. Note that signaling operations CSTi/CSTo do not function in the IMA Mode. The
Global Control Register 900 bit CK1 is ignored for this mode. 8.192 Mbit/s backplane mode is not
supported if IMA mode is selected on any of the framer’s.
not used.
G802 Mode. If set, this bit maps DSTi data channels transparently onto the transmit line data
and maps the receive data onto DSTo channels as per G.802.
Japan Yellow Alarm Set this bit high to select a pattern of 16 ones (111111111111111) as the
ESF yellow alarm. In order to transmit the japan yellow alarm the TESFYEL bit has to be set.
Transparent Mode Select. In transparent Mode the data present at the DSTi channels are
transparently sent to the T1 interface. The S bit from the DSTi interface (Channel 31 if running at
2.048 Mb/s backplane) is sent to the S bit position of the T1 interface.The rest of the channelized
data is sent unaltered to the T1 interface. Ensure that TCPI of per channel controlis not set.
T1DM Mode Select. Set this bit high to select T1DM Mode. In T1DM the Ft and Fs pattern is the
same as the D4 Mode but a 1011YR0 pattern is sent and detected in Channel 24 of the T1
interface. Bit Y is used to indicate a yellow Alarm and R bit is used by AT&T for a 8 Kb/s
communication channel.
Extended Super Frame. Setting this bit enables transmission and reception of the 24 frame
superframe DS1 protocol.
not used.
Cross Check. Setting this bit in ESF mode enables a cross check of the CRC-6 remainder
before the frame synchronizer pulls into sync. This process adds at least 6 milliseconds to the
frame synchronization time.
Reframe Select 1 - 0. These bits set the criteria for an automatic reframe in the event of framing
bits errors. The combinations available are:
RS1 - 0, RS0 - 0 = sliding window of 2 errors out of 4 frames.
RS1 - 0, RS0 - 1 = sliding window of 2 errors out of 5 frames.
RS1 - 1, RS0 - 0 = sliding window of 2 errors out of 6 frames.
RS1 - 1, RS0 - 1 = no reframes due to framing bit errors.
Note that for T1DM mode, the definition of frame boundary is starting from the channel 1 data
including the synchronization byte(10111YR0) and the following’ S’ bit. The Y and the R bits are
ignored for synchronization.
Fs Bit Include. Only applicable in D4 mode. Setting this bit causes errored Fs bits to be included
as framing bit errors. A bad Fs bit will increment the Framing Error Bit Counter, and will
potentially cause a reframe. The Fs bit of the receive frame 12 will only be included if D4SECY is
set. Note that when FSI bit is set both Ft and Fs are taken into consideration before declaration
of synchronization
Reframe. A 0 to 1 transition of this bit causes an automatic reframe.
Table 63 - Framing Mode Select (R/W Address Y00) (T1)
Zarlink Semiconductor Inc.
MT9072
Functional Description
116
Data Sheet